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Codasip delivers leading-edge processor IP and high-level design tools that provide system-on-chip designers with all the advantages of the RISC-V open-standard ISA, along with the ability to uniquely optimize the processor IP.

We currently offer several microarchitectural implementations of the RISC-V ISA with 1,3, and 5-stage pipelines. All are fully compliant with the RISC-V specification, and fully customizable. In addition to the base processor implementation, Codasip supports all optional instruction layers as defined by the current RISC-V specification.

Using Codasip Studio (an Eclipse-based integrated processor development environment), the processor is first described in a high-level description language called CodAL and then the tools automatically synthesize the design’s RTL, testbench, virtual platform models and processor SDK (C/C++ compiler, debugger, profiler, etc.). Time that would otherwise be required to maintain a complete SDK and implementation is significantly reduced thanks to the highly effective  and silicon-proven Codasip methodology.

Formed in 2006 and headquartered in Brno, Czech Republic, Codasip is a founding member of the RISC-V Foundation and has offices in the US and Europe, with representatives in Asia and Israel.