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Keynote: RISC-V, AI and Innovation
Making of the RISC-V Reader Japanese Translation
The Future of Broadcast and Broadband Services, and Expectation to Processors (Keynote Speech)
Japan Broadcasting Corporation Science & Technology Research Laboratories
AI-nization of Rakuten, Inc. (Keynote Speech)
AI Promotion Group, Rakuten
(Vector, TEE, Privileged, etc.)
Emerging AI, ML and DL applications represent a major inflection point that is revolutionizing architectural choices. These applications are growing fast and represent an accelerating opportunity for RISC-V. In ML, both for training and especially for inferencing, energy-efficiency with flexible performance vs power tradeoffs are required. Also, in ML, DL and other AI areas, algorithms are still undergoing rapid change. We believe that to keep from quickly becoming obsolete, that a combination of general purpose RISC-V processors with Domain Specific Accelerators will be a more stable long-term solution than fixed-function accelerators. Fixed function accelerators, such as a systolic array or data-flow type solutions are unlikely keep up with this fast pace of algorithmic change, and therefore fail to deliver high sustainable performance rates as algorithms change. We plan to build better solutions based on RISC-V that are configurable, scalable, and support fast algorithmic innovation by designers. RISC-V is a good baseline from which to build and deliver new, energy-efficient, configurable, flexible solutions, based on the industry-standard RISC-V ISA, to deliver compelling solutions for AI and ML.
Imperas launched the RISC-V Processor Developer Suite at the 7th RISC-V Workshop at Western Digital in Milpitas, CA. As 6 months is a long time in the RISC-V community and this update will highlight the new platform models and custom instruction support.
All paid attendees will receive a copy of the Japanese Edition of the RISC-V Reader ($20 value).