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Key Sessions

Dave Ditzel

Keynote: RISC-V, AI and Innovation

Esperanto Technologies

Andrew Waterman

Making of the RISC-V Reader Japanese Translation

SiFive

Masayoshi Onishi

The Future of Broadcast and Broadband Services, and Expectation to Processors (Keynote Speech)

Japan Broadcasting Corporation Science & Technology Research Laboratories

Masayuki Chatani

AI-nization of Rakuten, Inc. (Keynote Speech)

AI Promotion Group, Rakuten

Oct 18
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08:00 - 09:15 75 mins
Registration
09:15 - 09:30 15 mins
Welcome
  • Hideharu Amano - Professor, Keio University
09:30 - 09:40 10 mins
A Perspective on the Role of Open-Source IP In National AI Chip Electronics Projects
  • Hiroshi Fuketa - Deputy Manager, Commerce and Information Policy Bureau, MITI
09:40 - 09:55 15 mins
Introduction of Technologies and People Supporting RISC-V Ecosystem
  • @msyksphinz FPGA Diary Author, FPGA Diary Author
09:55 - 10:10 15 mins
Fedora on RISC-V -- Status and Plan
  • Wei Fu - Software Engineer, Red Hat
10:10 - 10:30 20 mins
Info
RISC-V Architecture Update (Vector, TEE, Privileged, etc.)
  • Krste Asanovic - Professor / Chief Architect, UC Berkeley | SiFive

(Vector, TEE, Privileged, etc.)

10:30 - 11:00 30 mins
Info
Keynote: RISC-V, AI and Innovation
  • Dave Ditzel - President and CEO, Esperanto Technologies

Emerging AI, ML and DL applications represent a major inflection point that is revolutionizing architectural choices. These applications are growing fast and represent an accelerating opportunity for RISC-V. In ML, both for training and especially for inferencing, energy-efficiency with flexible performance vs power tradeoffs are required. Also, in ML, DL and other AI areas, algorithms are still undergoing rapid change. We believe that to keep from quickly becoming obsolete, that a combination of general purpose RISC-V processors with Domain Specific Accelerators will be a more stable long-term solution than fixed-function accelerators. Fixed function accelerators, such as a systolic array or data-flow type solutions are unlikely keep up with this fast pace of algorithmic change, and therefore fail to deliver high sustainable performance rates as algorithms change. We plan to build better solutions based on RISC-V that are configurable, scalable, and support fast algorithmic innovation by designers. RISC-V is a good baseline from which to build and deliver new, energy-efficient, configurable, flexible solutions, based on the industry-standard RISC-V ISA, to deliver compelling solutions for AI and ML.

11:00 - 11:30 30 mins
Networking Break
11:30 - 11:45 15 mins
Security and Hypervisor: Hypervisor Extension
  • Andrew Waterman - Chief Engineer, SiFive
11:45 - 12:00 15 mins
Info
RISC-V Open-Source Models and Virtual Platforms Coupled with Commercial Grade Simulation Technologies and Tools
  • Shuzo Tanaka - VP and Director, eSOL TRINITY Co., Ltd.

Imperas launched the RISC-V Processor Developer Suite at the 7th RISC-V Workshop at Western Digital in Milpitas, CA.  As 6 months is a long time in the RISC-V community and this update will highlight the new platform models and custom instruction support.  

  • Commercially supported models, simulator and tools focused on RISC-V o High performance RISC-V simulator: >1000 MIPS 
  • All RISC-V features implemented in models 
  • Models easily user extendable: registers, instructions, behaviors 
  • CPU Model Code Coverage 
  • CPU Instruction Coverage 
  • CPU timing, power estimation 
  • Interfaces for use with 3rd party simulators, RTL testbenches 
  • Imperas processor verification tools 
  • Fixed Platform Kits for end users and ecosystem partners
12:00 - 12:15 15 mins
Info
Making of the RISC-V Reader Japanese Translation
  • Andrew Waterman - Chief Engineer, SiFive
  • Eiji Yokota - Managing Director, Cross Media Group, Nikkei BP Consulting,Inc.
  • Hideya Kawahara - Consultant, SH Consulting
  • Mitsuaki Narita - Translator, Independent
  • Eiji Kasahara - Member, Esperanto Technologies

All paid attendees will receive a copy of the Japanese Edition of the RISC-V Reader ($20 value).

12:15 - 12:30 15 mins
Embracing a System Level Approach in the Real World: Combining Arm & RISC-V in Heterogeneous Designs
  • Rupert Baines - CEO, UltraSoC
12:30 - 12:45 15 mins
Implementing 64-bit RISC-V Chip with MMU, L1 and L2 Using Academic Shuttle in Japan
  • Kesami Hagiwara - Professor, University of Electro-Communications
12:45 - 14:10 85 mins
Lunch
14:10 - 14:25 15 mins
RISC-V Asia Pacific Regional Marketing Activities
  • Alex Guo - RISC-V APAC Chair & RISC-V Day Shanghai Organizer, Jinglue Semiconductor
  • Naomi Tsujioka - RISC-V APAC Co-chair, SH Consulting
14:25 - 14:45 20 mins
The Future of Broadcast and Broadband Services, and Expectation to Processors (Keynote Speech)
  • Masayoshi Onishi - Deputy Manager, Japan Broadcasting Corporation Science & Technology Research Laboratories
14:45 - 15:15 30 mins
AI-nization of Rakuten, Inc. (Keynote Speech)
  • Masayuki Chatani - Executive Officer & GM, AI Promotion Group, Rakuten
15:15 - 15:45 30 mins
Networking Break
15:45 - 16:00 15 mins
Info
The Esperanto ET-Maxion High Performance Out-of-Order RISC-V Processor
  • Polychronis Xekalakis - CPU Architect, Esperanto Technologies
  • Christopher Celio - CPU Architect, Esperanto Technologies
16:15 - 16:30 15 mins
Extending RISC-V Solutions for AIoT
  • Charlie Su - CTO and SVP, Andes Technology Corporation
16:30 - 16:45 15 mins
Info
Mi-V Embedded Ecosystem
  • Krishnakumar Ranamoorthi - Sr. Staff Product Marketing, Microchip Technologies
16:45 - 17:00 15 mins
The SCR Family of RISC-V Compatible Processor IP
  • Alexander Redkin - Director, Syntacore
17:00 - 17:25 25 mins
Networking Break
17:25 - 17:45 20 mins
Opportunities and Challenges of Building Silicon in the Cloud
  • Krste Asanovic - Professor / Chief Architect, UC Berkeley | SiFive
17:45 - 18:00 15 mins
CloudBEAR Processor IP Product Line
  • Alexander Kozlov - CTO, CloudBEAR
18:00 - 18:15 15 mins
FIPS140-2 Compliant Trust Module for RISC-V Core Complex
  • Shumpei Kawasaki - Founder, SH Consulting KK
18:15 - 18:30 15 mins
OpenWrt Porting for RISC-V
  • Alex Guo - RISC-V APAC Chair & RISC-V Day Shanghai Organizer, Jinglue Semiconductor
18:30 - 18:45 15 mins
Performance and Cost Efficiency of Big-Endian on RISC-V
  • Akira Tsukamoto - Research Staff, AIST: National Institute of Advanced Industrial Science and Technology
  • Kuniyasu Suzaki - Senior Researcher, AIST: National Institute of Advanced Industrial Science and Technology
18:45 - 18:55 10 mins
Efforts of Linux Devian for 64-bit RISC-V (riscv 64)
  • Nobuhiro Iwamatsu - Software Developer, Debian Project