RISC-V Day Tokyo is part of the Informa Tech Division of Informa PLC
This site is operated by a business or businesses owned by Informa PLC and all copyright resides with them. Informa PLC's registered office is 5 Howick Place, London SW1P 1WG. Registered in England and Wales. Number 3099067.
Shumpei today leads SHC's development of FPGA/SOC processor platforms. Prior to co-founding SHC, Shumpei worked at Hitachi Semiconductor America (HSA), Renesas America (REA), and Hitachi Ltd in Japan. At HSA and REA, Shumpeiâ€™s team developed a Secure Operating System (OS) for Renesas's security chips. The Secure OS was used in authentication of smart phone accessories, automotive infotainment systems, routers, optical switches, and digital video recorders, and adopted by Renesas's competitors. During the same period, Shumpei's team developed audio / speech processing library used in automotive hands-free system, and connected navigation systems. Earlier at Hitachi Ltd., in 1989 Hitachi and Motorola ISA Dispute Shumpei worked on technical terms of settlement in 1990. Shumpei defined SH RISC CPU Instruction Set Architecture (ISA). In 1992 Shumpei along with 20 colleagues filed a 280 page patent, "Microcomputer having 16 bit fixed length instruction format", later called "2545 patent" or US5682545A leveraged by ARM Thumb. SH was used in embedded systems such as Sega game consoles, automotive Electronic Control Units (ECUs), and Japan's Shinkansen Bullet Train system and became #1 volume RISC CPU shipment for 1996-1997. Shumpei promoted partnerships with Cygnus Support (now Redhat) on GCC / Linux, Sun Microsystems (now Oracle) on Java OS, Microsoft on Windows CE / Automotive and .NET Micro Framework, and QNX on Neutrino OSes. Other work by Shumpei includes TRON floating-point accelerator used in Japan's national space program, and a never materialized AI32 AI language engine. Shumpei received B.A. in Math from Knox College and M.S. in Computer Science from University of Illinois at Urbana-Champaign.