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Welcome to the RISC-V Global Event Series: the official events for the RISC-V Foundation

Attend the first RISC-V Summit, 3-6 December in Silicon Valley!

ABOUT RISC-V


FREE, OPEN, SCALABLE, FLEXIBLE

The microprocessor IP market is being disrupted. RISC-V is an open, free instruction set architecture (ISA) enabling a new era of processor innovation through open standard collaboration.

The established world order of the silicon market is about to be overturned, and the implications of this change will resonate from Silicon Valley to Silicon Fenn and beyond.

Now is the time to engage with the ISA and its expansive ecosystem learn about its benefits, and understand the commercial implications for the strategy of your company and those of your competitors.

INTRODUCING WORLD-LEADING EVENTS FOCUSED ON RISC-V ISA.

RISC-V Day Tokyo

DATE: October 18, 2018
VENUE: Keio University; Tokyo Hiyoshi campus


RISC-V Summit, Santa Clara

DATE: December 3 - 6, 2018
VENUE: Santa Clara Convention Center Santa Clara, CA