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Welcome to the RISC-V Global Event Series: the official events for the RISC-V Foundation

ATTEND THE RISC-V SUMMIT 2018, DEC 3 - 6 2018, AND LEARN HOW THE FREE AND OPEN RISC-V ARCHITECTURE IS REVOLUTIONIZING THE SILICON MARKET AND BEYOND! Meet the RISC-V Community and Experience Four Days of Presentations on RISC-V ISA Architecture, Commercial and Open-Source Implementations, Software and Silicon, Vectors and Security, Applications and Accelerators, Simulation Infrastructure and Much More.

ABOUT RISC-V


FREE, OPEN, SCALABLE, FLEXIBLE

The microprocessor IP market is being disrupted. RISC-V is an open, free instruction set architecture (ISA) enabling a new era of processor innovation through open standard collaboration.

The established world order of the silicon market is about to be overturned, and the implications of this change will resonate from Silicon Valley to Silicon Fenn and beyond.

Now is the time to engage with the ISA and its expansive ecosystem learn about its benefits, and understand the commercial implications for the strategy of your company and those of your competitors.

INTRODUCING WORLD-LEADING EVENTS FOCUSED ON RISC-V ISA.

RISC-V Summit, Santa Clara

DATE: December 3 - 6, 2018
VENUE: Santa Clara Convention Center Santa Clara, CA

RISC-V Workshop Taiwan

DATE: March 12-14, 2019
VENUE:  National Tsing Hua University, Hsinchu, Taiwan

RISC-V Workshop Zurich

DATE: June 11-13, 2019
VENUE:  ETH Zurich, Zurich, Switzerland