Location: 2nd Floor Meeting Rooms 203/204
RISC-V Instruction Set Architecture has become a key driver for driving open source projects across wide gamut of end applications. Most recently we have seen a lot of application in the Internet of Things (IoT) segment, microcontrollers for a variety of traditional embedded applications, and applications requiring capability for low power operation of inference engines based on artificial neural networks.
In Western Digital, we have developed super-scalar (2-way) 9-stage pipeline mostly in-order, open-source core ECHX1, targeting in-house embedded Storage System on Chip (applications). In this paper, we plan to present some of the architectural details of the core, and challenges in the implementations, as well as discuss application of the core for the Flash controller. Additionally, we will explain the vision for expansion of RISC-V cores into datacenter and enterprise market.
We believe that open interface architectures will be key drivers of datacenter applications in 2023. We are witnessing computation shifting to dedicated machine learning and inference accelerators (also based on RISC-V Cores!) , and fast data migrating to large low latency, persistent memory pools. In this new world, the main processor interface connectivity capabilities, in particular bandwidth, latency and cache coherence capability for efficient memory sharing are becoming more relevant than raw compute capability of the cores.
We will discuss open interfaces for persistent memories, such as JEDEC-standardized NVDIMM-P (Non-volatile dual inline memory module for persistent memories), and also exporting cache-coherence protocols (such as Tilelink) over ubiquitous fabrics such as Ethernet. We plan to discuss details of the MPF4brik â€“ memory protocol fabrik, which exposes Tilelink on the Ethernet, and allows smart switching using P4-based programmable networking. We are envisioning low-cost SMP (symmetric multiprocessing) architectures based on open standards, which will enable hyperconvergence of processing and memory in the future datacenter.