2019 Date And Venue Will Be Announced Soon
The RISC-V Revolution!
Thanks for attending the RISC-V Workshop Barcelona! Join us at the next event and be part of the disruptive force transforming the microprocessor IP market through open standard collaboration
The Next RISC-V Workshop Will Take Place In Chennai, 18 - 19 July 2018 At The Indian Institute of Technology Madras, Chennai
The RISC-V Workshop Barcelona
The microprocessor IP market is being disrupted, and RISC-V is fast gaining support as an attractive license-free approach to architecture. This open standard collaboration will transform and reshape established world order of the silicon market, and the implications of this change will resonate from Silicon Valley to Silicon Fenn and beyond. Now is the time to explore this disruptive technology, learn about its benefits, and understand the commercial implications for the strategy of your company and for those of your competitors. Join the expansive and international RISC-V ecosystem to discuss current and prospective RISC-V projects and implementations, as well as influence the future evolution of the instruction set architecture (ISA).
Event Highlights At RISC-V Workshop Barcelona 2018
RISC-V ISA Extensions Update
A half-day of tutorials from the working groups of the RISC-V technical committee on the latest updates around such topics as Base ISA Ratification, BitManip, Compliance, Debug, Formal Spec, Memory Model, Opcode Space Management, Privilege Spec, Security, Software Toolchain and/or Vector Extensions.
2 Day Workshop
Two full days of presentations on RISC-V architecture, commercial and open-source implementations, software and silicon, vectors and security, applications and accelerators, simulation infrastructure and much more.
Leaders in the Ecosystem
Speakers included leaders from the major players in the RISC-V ecosystem, including the leading technology companies and research institutions driving the RISC-V ISA specification.
Parties, Networking & Demo Zone
Networking reception with poster sessions and demos where delegates were able to mix, mingle and share a drink with peers, while learning about the latest implementations and updates of the technology. Plus delegates were able to stop by the demo zone and explore the latest innovations on the market.
Tour the Barcelona Supercomputing Center!
Several tours of the Barcelona Supercomputing Center took place during the networking reception. The BSC is located in a former chapel and was featured in Dan Brown's science fiction thriller origin.
Member Meetings
Reserved for members of the RISC-V Foundation.
Thanks to our organisers
The RISC-V Barcelona Workshop was made possible with the cooperation and support of the Universitat Politècnica de Catalunya and the Barcelona Supercomputing Centerand the program committee:
Universitat Politècnica de Catalunya and the Barcelona Supercomputing Center Organizers:
Eduard Ayguadé, BSC & UPC
Mateo Velero, BSC & UPC
Fabrizio Gagliardi, BSC & UPC
Lourdes Cortada, BSC
Nuria Sirvent, BSC
Program Committee:
Chair: Roger Espasa, Esperanto Technologies
Vice Chair: Yunsup Lee, SiFive
Producer: Tami Carter, Informa
Luca Benini, ETH Zrich
Zvonimir Bandic, Western Digital
Steve Pawlowski, Micron
Don Stark, Google
Jesus Labarta, BSC
Dan Lustig, Nvidia
Charlie Hong-Men Su, Andes Technology
Rick O’Connor RISC-V Foundation