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Key Sessions

Vivek Tyagi

Keynote: RISC-V: Enabling a New Era of Open Data-Centric Computing Architectures

Sandisk Western Digital

July 18, 2018
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8:00am - 8:10am 10 mins
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8:10am - 8:55am 45 mins
Registration & Breakfast
8:55am - 9:00am 5 mins
Welcome address and about the workshop
  • Kamakoti Veezinathan - Professor, IIT Madras
  • G S Madhusudan - CEO and Co-Founder, InCore Semiconductors
9:00am - 9:15am 15 mins
RISC-V ISA & Foundation Overview
  • Rick O' Connor - Executive Director, RISC-V Foundation
9:15am - 9:30am 15 mins
RISCV ISA: Understanding Limitations and Methods to Improve Code Density & Performance
  • Gnanasekar Rajakumar - Technologist, Western Digital
  • Ravikumar Gaddam - Staff Engineer, Western Digital

RISC-V is an Open Architecture with Instruction Set designed for extensions from the get go. The core RISC-V Instruction Set is fairly small and it is independent of any micro-architecture or implementation style. In this study, we focused on RISC-V ISA and RISC-V Tool chain performance for ultra-low cost embedded applications. For these applications, we have chosen to investigate the RV32IMC flavor of RISC-V. The extensions were chosen with view to obtain better performance for small systems. We define the key metrics used to evaluate and assess the code density. 

In this study, we have also come up with list of benchmarks and applications that we used to evaluate the architecture and tool chain. We present extensive data based on our analysis and finally make recommendations on the tool chain and ISA updates. 

We will present: 

  • Key Performance Indicators (KPIs) for ultra-low cost embedded applications.
  •  Results of GNU C Compiler and LLVM C Compiler tool chain from Code Density and Performance perspective (RISCV Architecture). 
  • Results of GNU C Compiler tool chain from Code Density perspective for ARM Architecture. Benchmarks like coremark, dhrystone (which tend to be short) and snippets from typical Storage code (which gives deeper understanding of more real time use cases) were used for the study. 
  • Analysis and Recommendations for ISA extensions.
  • Analysis and Recommendations for Tool Chain improvements. 
  • How to exploit Machine Learning techniques to study code density and performance in greater detail.

Kalpesh Mehta – Senior Director , Flash Products Group, Western Digital
Vimal Jain – Director, Flash Products Group
Gnanasekar Rajakumar – Technologist, Western Digital
Ravikumar Gaddam – Staff Engineer, Western Digital

9:30am - 10:00am 30 mins
Going Beyond the RISC-V General Purpose Solutions
  • Neel Gala - CTO, InCore Semiconductors Pvt. Ltd.

Processors built using the RISC-V ISA are known to be successful in the embedded/IoT domain and are heading to replace the dominance of ARM-based solutions in such applications. However, market trends show that general purpose cores will no longer survive the compute, power and performance needs of today's applications. With this in mind, InCore focuses in providing customized core/SoC solutions in the IoT sector in 3 primary domains: Security, Reliability and Intelligence. The vision is to treat security, reliability and intelligence as first-class citizens while designing RISC-V processors. This paper highlights some of the efforts undertaken by InCore in each of these verticals.

10:00am - 10:30am 30 mins
Architecture Exploration of RISC-V Processor and Comparison with ARM Cortex A53 and A72
  • Karthikeyan Sugumaran - Architecture Modeling Intern, Mirabilis Design
  • Tom Jose - Application Specialist, Mirabilis Design

This research project is focused on the architectural exploration of RISC-V ISA based processor for networking architectures such as a Router, using the trade-off between power consumption and performance. The optimized architecture is compared against commercially available RISC processors from ARM.

10:30am - 11:00am 30 mins
Networking Break
11:00am - 11:30am 30 mins
It's Not About the Core, It's About the System
  • Gajinder Panesar - CTO, UltraSoC

RISC-V is no longer just a core in the hands of academics and researchers. Consumers of these cores are now realising, that it is not just about the core, it's about the system.  There is now a great deal of momentum behind RISC-V with companies building real systems of varying degrees of complexity. These systems are architected with several, sometimes even 1000s of heterogeneous processor cores -- RISC-V and others -- and many tens of other IP blocks. The software executing on such systems will be large and complex having been produced by large teams across the world.   To make such systems realistic and usable, a holistic approach is needed to debug and analysis. This needs to be a system-wide approach, one which provides a coherent view of all the components within a SoC. It has to be joined up with cores, providing run-control as well as processor trace, and interconnects that non-intrusively monitor and analyze the device's internal behavior at wire speed and in the field.  We present just such a debug and analytics approach, one that has been deployed in several commercial systems and one which is greatly enhancing the RISC-V ecosystem, which is extremely important for its success. Using our heterogeneous demonstration platform, we will show this in operation.

11:30am - 11:45am 15 mins
RiTA: RISC-V Trace Analyzer
  • Anmol Sahoo - Project Associate, IIT Madras
  • Neel Gala - CTO, InCore Semiconductors Pvt. Ltd.

Keeping in line with the vision of customizing RISC-V processors for optimum performance in specific workloads, it becomes important to obtain various statistics about program execution at the instruction level. RiTA is a simple Python tool that takes a step in this direction by analyzing the log file dumped by spike, the ISA simulator and then returning various descriptive statistics about the code. This presentation documents the basic architecture of RiTA and describes the existing and planned features.

11:45am - 12:10pm 25 mins
Keynote: RISC-V: Enabling a New Era of Open Data-Centric Computing Architectures
  • Vivek Tyagi - Head Sales, Sandisk Western Digital
12:10pm - 1:30pm 80 mins
Networking Lunch
1:30pm - 2:00pm 30 mins
Accelerating the RISC-V Revolution: Unleashing Custom Silicon with Revolutionary Design Platforms and Custom Accelerators
  • Huzefa Cutlerywala - Director, Business Development, Open Silicon | a SiFive Company

Open source has revolutionized software. Now, it's hardware's turn. In this talk, I present the innovation opportunities being unleashed by making custom chips with the next generation of Freedom Platforms. I will demo our Linux-capable HiFive Unleashed board, expansion kit, and the latest AI accelerators in the ecosystem to showcase how RISC-V can be easily customized around the Freedom Unleashed Platform.

2:00pm - 2:15pm 15 mins
Mi-V RISC-V Embedded Ecosystem
  • Krishnakumar Ranamoorthi - Sr. Staff Product Marketing, Microsemi

This presentation will showcase the growing ecosystem being built for embedded RISC-V on Microsemi's FPGA portfolio. The ecosystem includes Soft RISC-V CPUs, Design and development tools, Operating systems, Evaluation boards, and solutions such as Linux PC and Deep Learning implemented on our Mi-V Unleashed expansion board and the SiFive Unleashed board. Also introducing X-WARE IoT Platform solution from expresslogic.

2:15pm - 2:30pm 15 mins
Verification of the PULPino SoC platform using UVM
  • Mahesh R - Associate Engineer, Cisma Consultants Pvt Ltd
  • Shamanth HK - Associate Verification Engineer, Cisma Consultants

As RISC-V gains popularity and its use in semiconductor devices grows, it becomes increasingly important to start looking at verification of these SoCs based on RISC-V. An SoC is typically characterized by the processor (RISC-V) and an associated set of peripheral devices on chip. It is not uncommon to find an SoC having communication links to external world through interfaces such as USB, SPI, i2C etc. Verification of these SoCs offer several challenges, the chief among them being the hardware-software interface between the software test code running on the CPU and the hardware external peripherals such as SPI slave. Although several verification techniques exist the Universal Verification Methodology is currently becoming the standard among all semiconductor companies. In this project we have verified the RTL of the PULPino platform using UVM.

2:30pm - 2:45pm 15 mins
Porting Graphical Stacks to RISC-V using QEMU and Yocto
  • Atish Patra - Principal R&D Engineer, Western Digital

For RISC-V to compete with other incumbent architectures outside of the very small single-use embedded space it will need support to run a Graphical User Interface (GUI). Even in embedded devices users are accustomed to easy to use GUIs such as that presented by Android and iOS.  With the rise of open source software and people becoming increasingly privacy conscious, there is a growing number of open source smartphone software stacks that compete against Android and iOS. Plasma Mobile is one example of a complete software system for mobile devices with a strong focus on users' privacy protection. It has an active development community behind it, backed by the KDE desktop environment project developers and is running on real ARM hardware today.  

This presentation explores the process of building Plasma Mobile for RISC-V using Yocto. Yocto is a Linux Foundation backed project whose goal is to allow the creation of Linux distributions specifically for embedded devices. This requires cross compiling the entire dependency chain from QT5 and Xorg to Plasma.  

We also discuss testing of this mobile environment using the RISC-V model in QEMU, including a PCIe attached GPU. This allows easy development and testing without RISC-V hardware. QEMU has a much quicker turnaround time than real hardware allowing faster development cycles. As an additional advantage QEMU has been setup to model the RISC-V hardware, allowing a quick and easy transition to running the software stack on hardware when a GPU becomes available.  

This presentation will walk through the changes required to Yocto and the corresponding software projects to cross compile the full Plasma Mobile stack to for RISC-V and get a graphics stack up and running. It will also detail additional work done to ensure that the required kernel drivers are enabled and that the correct configuration is used.We will also discuss the changes to QEMU to allow this testing, along with  current limitations and what can be done in the future to improve the RISC-V ecosystem.

2:45pm - 3:15pm 30 mins
Networking Break
3:15pm - 4:15pm 60 mins
Panel: Evolving a RISC-V based Ecosystyem in India
  • Panelist Vivek Tyagi - Head Sales, Sandisk Western Digital
  • Panelist Konala Varma - Business Head - Smart Devices, Intel
  • Panelist Mahesha Nanjundaiah - Director, HPE Research, HPE
  • Panelist Asutosh Upadhyay - Head - Programs, Axilor Ventures
  • Panelist Amudhan Balasubramanian - General Manager, HCL Technologies
  • Moderator G S Madhusudan - CEO and Co-Founder, InCore Semiconductors
4:15pm - 5:00pm 45 mins
Poster / Demo Previews
  • Andrea Bocco - PhD Candidate, CEA-Leti
  • Shubhodeep Choudhury - CEO, Valtrix
  • Tiago Jost - Ph.D. Candidate, ENS Paris and CEA
  • Kevin McDermott - CTO, Imperas Software
  • Atish Patra - Principal R&D Engineer, Western Digital
  • Gajinder Panesar - CTO, UltraSoC
  • Variable Precision RISC-V Co-processor for Scientific Applications, Andrea Bocco & Tiego Trevian Jost, CEA LETI 
  • RVS - A Verification Suite to Test Compliance with RISC-V Architecture,  Shubhodeep Roy Choudhury 
  • RISC-V open-source models and virtual platforms coupled with commercial grade simulation technologies and tools, Kevin McDermott, Imperas 
  • Multi-level Interrupt Design in RISC-V Linux, Atish Patra, Western Digital
  • Demo Table Preview, Western Digital
  • Demo Table Preview, Microsemi
  • Demo Table Preview, IIT Madras
  • Demo Table Preview, UltraSoC
5:00pm - 8:00pm 180 mins
Evening Reception, Poster Sessions and Demos