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July 19, 2018
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8:00am - 8:10am 10 mins
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Download the Proceedings for the RISC-V Workshop Chennai

Looking for the workshop shop slides? They are available for download here.

8:10am - 9:00am 50 mins
Registration & Breakfast
9:00am - 9:30am 30 mins
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RISC-V Software Development Methodology for RISC-V Devices with RTOS and Linux or Both
  • Kevin McDermott - CTO, Imperas Software

As RISC-V based devices start to appear in the market many software development project will start to focus on the details around porting of various OS and RTOS plus the associated work on driver development and bring up of legacy software. The key to the success of RISC-V will be the support and tools needed to drive broad adoption throughout the embedded software developer community.  The embedded systems community is increasingly complementing hardware-based software development with virtual prototypes to achieve higher software quality and reduce software engineering schedules.  Virtual platforms, offer advantages over hardware based development platforms in controllability, observability, repeatability, and ease of automation.  Plus virtual platforms can also be available to the entire software team months before hardware platforms can be used, so provide an early start for software tasks.   At a higher level than the actual development platforms, embedded software teams are also using Agile methodologies, including Continuous Integration (CI).  This modern methodology for embedded software development, debug and test will be discussed and the complementary nature of virtual and hardware platforms will be shown.  Including the bring up of FreeRTOS on a RV32I platform and also Linux with an example application utilizing custom instructions.

9:30am - 10:00am 30 mins
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Linux Kernel on RISC-V: Where do we stand?
  • Atish Patra - Principal R&D Engineer, Western Digital

The momentum behind RISC-V ecosystem is really commendable and its open nature has a large role in its growth. It allowed contributions from both academic and industry community leading to an unprecedented number of hardware designs proposals in a very short span of time.  However, RISC-V software ecosystem also need to grow across the stack so that RISC-V can be a true alternative to existing ISA. Linux kernel support holds the key in this. This talk will serve two goals. First, it will summarize the current capabilities of Linux on RISC-V to guide application developers toward appropriate design choices for early prototyping and performance benchmarking. And second, the presentation will help to guide new developers willing to start contributing towards the RISC-V kernel port and its ecosystem by pointing out areas of the support lacking or in need of more work. As a conclusion to this presentation, we will also share our RISC-V experience, the difficulties encountered and how they were resolved to help other developers a faster transition to this exciting new architecture.

10:00am - 10:30am 30 mins
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A Comprehensive Framework For Power-based Side-channel Leakage Evaluation of SHAKTI C-Class
  • Muhammad Arsath - Student, IIT Madras
  • Chester Rebeiro - Assistant Professor, Indian Institute of Technology Madras

This work proposes a framework for evaluating data-leaks on SHAKTI C-Class (a RISC-V based microprocessor) through power-consumption side-channels. The work provides a comprehensive analysis of various metrics and techniques that have been proposed in literature to analyse data leaks due to such side-channels. The evaluation is done using a novel framework based on a Hamming Distance metric for modelling power patterns on binary data. The work further explores the cause of such data leaks and identifies architectural designs and practices which lead to such data leakages in the context of SHAKTI C-Class processor.

10:30am - 11:00am 30 mins
Networking Break
11:00am - 11:30am 30 mins
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RISECREEK: From RISC-V Spec to 22FFL Silicon
  • Vinod Ganesan - Student, IIT Madras
  • Gopinathan Muthuswamy - Project Associate, IIT Madras

SHAKTI is a series of micro-processor SoCs which target various applications ranging from small micro-controllers to server class applications. This paper describes the first Shakti SoC, code-named "Risecreek", that has been taped out on Intel's 22nm technology node. Risecreek is a test SoC designed around the open-sourced Shakti-C64 which is a 64-bit, 6-stage in-order pipelined microprocessor. It implements the RISCV-ISA and supports RV64IMAFD in- struction set (user specification v2.2). The microprocessor has a Memory Management Unit that supports sv39 vital- ization scheme and is compliant with the RISC-V privilege specification v1.10. The microprocessor includes a bimodal Branch Predictor Unit (BPU) with a Return Address Stack (RAS), 32KB Virtually Indexed Physically Tagged (VIPT) I-cache and D-cache, multi-cycle Single Precision (SP) and Double Precision (DP) Floating Point Units (FPU), and an AXI4-bus fabric for the peripherals. The various peripher- als that are integrated on the Risecreek SoC include I2Cs, QSPIs, UARTs, Timer, Platform Level Interrupt Controller (PLIC), JTAG controller, SDRAM controller, multi-channel DMA and also a custom expansion peripheral to connect to an FPGA. The complete SoC was designed using Bluespec System Verilog (BSV) and includes no 3rd party IPs. All pe- ripherals, controllers, engines are home-grown/modified and open source on the SHAKTI bitbucket repository.

11:30am - 12:00pm 30 mins
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Shakti M-Class Libre RISC-V SoC
  • Luke Leighton - Software Libre Engineer and Advocate, Independent

Most commercial mass-volume processors are designed based on reducing each of hard macro licensing cost, royalties, and risk.  Proprietary hard macros are chosen based on the fact that they are tried-and-tested.  Unfortunately the software libraries they come with are often also proprietary, particularly in the 3D and Video space.  The Shakti Group however has an over-riding requirement that the entire hardware design files and associated software drivers must be entirely libre-licensed, so that it may be independently audited, to ensure no spying back-doors in the hardware, or trojans built-in to the proprietary software.  This paper therefore outlines a plan on how to design and bring to market a mass-volume commercial System-on-a-Chip that prioritises BSD-licensed hard macros at the top of the list.

12:00pm - 12:30pm 30 mins
Info
SLSV : The Shakti LockStep Verification Framework
  • Paul George - Project Associate, IIT Madras
  • Lavanya Jagan - Project Associate, IIT Madras

The Shakti LockStep Verification (SLSV) Framework is a Dynamic Verification and post-silicon Validation Framework for RISC-V System on Chip solutions. SLSV allows designers to perform functional verification with directed and random test vectors against target device(s) under verification (DUV) right from RTL to Silicon. SLSV tracks relevant architectural and micro-architectural states and evaluates them against a specified golden model. The golden model can be a functional simulator/emulator or a synthesizable formal model. SLSV can presently operate with any RISC-V design with an SLSV compatible interface and currently supports designs compliant to the debug spec 0.13.  The benefit of SLSV lies in the customizability of the coverage metrics & model checkers  being observed by the user. SLSV provides a configurable script-like interface enabling the user to configure and track different micro-architectural states. SLSV further empowers quick fault localization and thereby speed-up RISC-V compliance.  SLSV is a completely open-source framework being developed at IIT-Madras and can be found at : github.com/command-paul/slsv-master

12:30pm - 2:00pm 90 mins
Networking Lunch
2:00pm - 2:30pm 30 mins
Info
A Survey of E31 RISC-V Core Floor-Plan and Its Impact on Power, Performance and Area (PPA)
  • Kunal Ghosh - Director, VLSI System Design Corporation Pvt. Ltd.
  • Anagha Ghosh - Director, VLSI System Design Corporation Pvt. Ltd.

E31, a RISC-V core from SiFive Inc., has an instance count of about 112k post synthesis, excluding memories. Due to huge instance count, the turn-around time for any PNR tool will be large, leading to delays in final SoC tape-out. In this paper, we did a survey of modularizing E31 core, pre-placing these new mid-size modules with fixed pin locations and leveraging hierarchical PNR feature of an EDA tool. Results shows, this approach reduces the turn-around time by more than 80%, while ensuring a similar/better PPA of entire core compared to flat PNR approach. This paper uses all open-source EDA toolset from opencircuitdesign.com, and 0.18um   technology node from OSU standard cell library.

2:30pm - 3:00pm 30 mins
Info
Integrating Gen-Z in Server-Class RISC-V Processors
  • Mohan Pathasarathy - Technical Architect, HPE

Gen-Z is a new open systems Interconnect created to provide memory semantic access to data and devices via direct-attached, switched for fabric topologies, and will accelerate the adoption of rack level composability. This talk will cover an overview of Gen-Z, and focus on implications for processors. A native implementation of Gen-Z will place requirements on the processor architecture, and we will explore some of these areas like number of lanes to be supported, memory mapping using ZMMUs, Gen-Z atomics and security features like page level encryption.

3:00pm - 3:30pm 30 mins
Info
Formal Specification of the RISC-V Instruction Set Architecture
  • Rishiyur Nikhil - Chief Technology Officer, Bluespec
  • Niraj Sharma - Head, India, Bluespec

The ISA Formal Specification Task Group was created by the RISC-V Foundation. In this talk, we describe what is a formal spec, its purpose, and how it will be used by verifiers, compiler writers and hardware designers, not only as an unambiguous and precise reference, but also to formally prove correctness of the artifacts they are designing.  We describe the subtleties induced by requiring ``universality'' (model all possible RISC-V implementations), modularity (many RISC-V features are optional extensions), and concurrency (non-determinism due to the Weak Memory Model interacting with optimizations such as pipelining, speculation, and cacheing).

The Task Group is pursuing several approaches; we will show excerpts, describe how to use it as an executable 'golden reference model', and describe how it is already being used by some groups in design and verification.

3:30pm - 3:45pm 15 mins
RISC-V Workshop Chennai Conclusion
  • Rick O' Connor - Executive Director, RISC-V Foundation