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Dates for the RISC-V Workshop Taiwan 2020 to be announced soon



RISC-V Workshop Taiwan

The microprocessor IP market is being disrupted, and RISC-V is fast gaining support as an attractive license-free approach to architecture. This open standard collaboration will transform and reshape established world order of the silicon market, and the implications of this change will resonate from Silicon Valley to Silicon Fenn and beyond.  Now is the time to explore this disruptive technology, learn about its benefits, and understand the commercial implications for the strategy of your company and for those of your competitors.  Join the expansive and international RISC-V ecosystem to discuss current and prospective RISC-V projects and implementations, as well as influence the future evolution of the instruction set architecture (ISA).

Ted Speers

Board of Directors, RISC-V Foundation and head of product architecture and planning

Microsemi’s SoC Group

“RISC-V Workshops are key events for connecting with a growing ecosystem committed to the success of the RISC-V ISA, and understanding the potential of RISC-V now and in the future. I strongly encourage anyone involved in the business of designing microelectronic systems – both members and non-members alike – to attend the upcoming RISC-V Workshop in Taiwan to learn more about how the RISC-V ecosystem is enabling a new era of processor innovation through open standard collaboration.” 


In-depth Technical Education
In-depth Technical Education

Two full days of presentations and updates on the RISC-V architecture, commercial and open-source implementations, software and silicon, vectors and security, applications and accelerators, simulation infrastructure and much more.

Leaders in the Ecosystem
Leaders in the Ecosystem

The speaking lineup will include leaders from the major players in the RISC-V ecosystem, including the leading technology companies and research institutions driving the RISC-V ISA specification.


No RISC-V Workshop is complete without our networking lunches & breaks where you can take time to relax and mingle with your peers.

Watch Highlights of the RISC-V Summit 2018

Watch highlight of the first annual RISC-V Summit which took place Dec. 3-6, 2018 at the Santa Clara Convention Center. There were more than 1,100 registrants from 32 countries around the globe. The Summit’s Exhibit Hall featured 29 exhibitors, with an impressive 53 presentations across the two days, as well as a hackathon.

Hear Charlie Su, CTO and SVP of Andes Technology present on New Members of AndeStar V5 Processor IPs.

Video highights taken from RISC-V Summit 2018. 

Attend the RISC- V Workshop Taiwan and hear Charlie Su, CTO and SVP of Andes Technology, present on New Members of AndeStar V5 Processor IPs. The presentation will provide you with an update of AndeStar V5 processor solutions with new features and more benchmarking data. In addition, Charlie Su will introduce a couple new V5 processor IPs to further broaden AndeStar support to the RISC-V community.

The presentation takes place on March 12th