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Key Sessions

Calista Redmond

Guiding the Future of RISC-V

RISC-V Foundation

Luca Benini

Energy efficient computing from Exascale to MicroWatts: The RISC-V playground

ETH Zurich

Krste Asanovic

RISC-V State of the Union

UC Berkeley | SiFive

June 11, 2019
Show Filter
08:00 - 09:00 60 mins
Registration & Networking
09:00 - 09:15 15 mins
Keynotes
Guiding the Future of RISC-V
  • Calista Redmond - CEO, RISC-V Foundation
09:15 - 09:40 25 mins
Info
Keynotes
Energy efficient computing from Exascale to MicroWatts: The RISC-V playground
  • Luca Benini - Professor, ETH Zurich

The twilight of Moore's Law and the explosive growth of Machine Learning workloads across the full range of the computing spectrum have created a tremendous window of opportunity for innovation in digital circuits and systems. The open RISC-V ISA is a major opportunity multiplier, as it unlocks holistic, cross-layer approaches for achieving energy efficiency and enables the creation of a fertile open innovation environment. The PULP open platform, based on the RISC-V ISA, was created to foster open innovation in computing and achieve energy efficiency and proportionality from high-performance processors and accelerators to microWatt near-sensor processing engines: the talk will give a view on the key milestones, the insight gained and the vision for the future.

09:40 - 10:05 25 mins
Official RISC-V Foundation Updates
RISC-V State of the Union
  • Krste Asanovic - Professor / Chief Architect, UC Berkeley | SiFive
10:05 - 10:20 15 mins
Official RISC-V Foundation Updates
RISC-V Technical Committee Update
10:20 - 10:35 15 mins
Official RISC-V Foundation Updates
RISC-V Marketing Committee Updates
  • Ted Marena - Chairman, RISC-V Marketing Committee | Director, RISC-V Ecosystem, Western Digital, RISC-V Foundation
10:35 - 11:05 30 mins
Networking Break
11:05 - 11:30 25 mins
Keynotes
Lead Sponsor Keynote
11:30 - 11:45 15 mins
Info
RISC-V Projects
OpenPiton+Ariane: The First Linux-Booting Open-Source RISC-V Manycore
  • Jonathan Balkind - Ph.D. Candidate, Princeton University
  • Michael Schaffner - Postdoctoral Researcher, ETH Zurich

We present OpenPiton+Ariane, the first Linux-booting, open-source, 64-bit RISC-V system that scales from single-core to manycore. OpenPiton+Ariane is a joint open-source effort between the Princeton Parallel Group led by David Wentzlaff, and the Digital Circuits and Systems Group of ETH Zürich led by Luca Benini. The latest update of the open-source Ariane processor (Ariane 4.1) now provides full support for the P-Mesh cache system from OpenPiton. Likewise, OpenPiton release 11 contains all required peripherals to host a 64-bit application processor with full SMP Linux support. Several build flows for small and large FPGA boards are available, enabling the prototyping of small single and dual-core configurations up to large manycore instances with 16 cores. In this talk, we will walk the audience through the system architecture and the modifications that were necessary to combine the two open-source projects. Further, we will present synthesis and performance results on recent FPGA platforms and explain how to get started with the framework.

11:45 - 12:00 15 mins
Info
RISC-V Projects
efabless' Raven: PicoRV32 on an ASIC, Open Source, Open Silicon
  • Tim Edwards - Senior Vice President of Analog and Design, efabless Corporation
  • Mohamed Kassem - Co-Founder and CTO, efabless

efabless, a fabless semiconductor company dedicated to creating an online community for ASIC designers has designed and fabricated a proof-of-concept RISC-V processor based on the PicoRV32 architecture.  The purpose of the design is to validate the use of open source tools on a web-based platform and to work as a reference design for anyone in the efabless community to redesign to their own custom specifications and incorporate their own choice of IP blocks.  The Raven chip is an SoC based around the PicoRV32 processor and includes analog functions such as a DAC, ADCs, bandgap reference, and RC oscillator;  and digital functions including an SPI flash driver, UART, and general-purpose I/O.  The core clock rate of the device is 100MHz.  Chip-level netlists and layout are open source.

12:00 - 12:15 15 mins
Info
RISC-V Projects
PULP-NN: An Open-Source Library for Deeply-Embedded and Quantized Neural Networks (QNNs) on a RISC-V Based Parallel Ultra Low Power Cluster
  • Angelo Garofalo - Ph.D. Student, University of Bologna
  • Luca Benini - Professor, ETH Zurich

Deep Neural Networks (DNNs) are gaining a key role in the IoT applications domain such as embedded computer vision, speech recognition, and detection problems. However, IoT devices such as MCUs, feature limited computational capabilities and on-chip memory, making necessary the software to be optimized and memory-aware. A recent trend to reduce DNNs memory footprint exploits the quantization of the network weights and activations. As such, ARM implemented a software library, CMSIS_NN, which provides software kernels for Quantized neural networks (QNNs) inference, targeting 16-bit and 8-bit operands. In this talk, we present an optimized software library to deploy DNNs on a parallel ultra-low-power tightly coupled cluster of eight RI5CY processors which are compliant with the RISC-V RV32IMFC specification and feature Xpulp ISA extension targeting digital signal processing.  The library contains a full set of kernels and utilities and fully exploits both the digital signal processing (DSP) extensions available in the processors and the cluster's parallelism, improving performance by up to almost two orders of magnitude with respect to a plain implementation on a single RISC-V core without extensions. The proposed library also achieves major energy efficiency improvements (2x).

12:15 - 12:30 15 mins
Info
RISC-V Projects
Bit by bit - How to fit 8 RISC-V cores in a $38 FPGA board
  • Olof Kindgren - Senior Digital Design Engineer, Qamcom Research & Technology

The RISC-V SoftCPU contest gave birth to a number of new RISC-V designs, many of which had novel ideas. One design called SERV (SErial RiscV) was special enough to win the jury's creativity award.  This presentation takes a look at the joy and challenges, the ideas and raw numbers of building a minimal bit-serial RISC-V implementation that is capable of booting Zephyr OS.

12:30 - 13:30 60 mins
Networking Lunch & Table Tops Visit
13:30 - 13:55 25 mins
Info
Security
OpenSBI Deep Dive
  • Anup Patel - Technologist, Western Digital

The RISC-V Open-source Supervisor Binary Interface (OpenSBI) project aims to provide an open and extensible implementation of the RISC-V Supervisor Binary Interface (SBI). Hardware and System-on-chip vendors can create their own SBI compliant runtime firmware using OpenSBI static library or use OpenSBI reference firmware as their SBI compliant runtime firmware.  Currently, the OpenSBI supports QEMU virtual machine, QEMU sifive_u machine, SiFive FU540 Unleashed board and Kendryte K210 board. The OpenSBI reference runtime firmware fit quite well with existing boot-flow of QEMU and SiFive FU540 Unleashed board. Booting Linux kernel directly as payload of OpenSBI reference runtime firmware is also supported (similar to RISC-V Berkely Bootloader (RISC-V BBL)). In the future, more reference runtime firmware can be added to OpenSBI to suit different types of boot-flows.  Going forward, OpenSBI can be used to prototype and validate extensions to the SBI base specifications which is now being drafted.  This talk will provide a detailed view of OpenSBI features, design, and implementation.

13:55 - 14:10 15 mins
Info
Security
Secure Bootloader for RISC-V
  • David Garske - Sotware Engineer, wolfSSL Inc.
  • Daniele Lacamera - Software Engineer, wolfSSL Inc.

wolfBoot is a portable, OS-agnostic, secure bootloader for microcontrollers, supporting firmware authentication and firmware update mechanisms.  This session will cover the porting of wolfBoot to RISC-V for implementing a secure bootloader and firmware update mechanism. All source code and example will be available on our GitHub repository here: https://github.com/wolfSSL/wolfboot Presentation will be done by David Garske, with coding and preparation assistance from Danielle Lacamera.

14:10 - 14:25 15 mins
Info
Security
An Open Source Approach to System Security
  • Helena Handschuh - Chair of the RISC-V Foundation Security Standing Committee | Fellow, Rambus

RISC-V provides a relative "clean slate" when it comes to designing secure systems. While specific use cases may end up with proprietary security measures to address the particular needs of that system, general security measures can benefit from an open source approach. It's common knowledge that sharing specifications with peers can advance development and testing more effectively than most proprietary methods. But where do you draw the line between developing your own security measures and contributing to the common good? What frameworks are required to ensure that the most sensitive parts of the system are protected while leaving some security aspects more open? This talk by Rambus Security Technologies Fellow, Helena Handschuh, will discuss these issues and ways that the RISC-V Foundation's Security Standing Committee is leading initiatives to ensure appropriately secured cores.

14:25 - 14:50 25 mins
Info
Posters
60 Second Poster Preview Sessions
  • Pieter Willems - Director Sales and Marketing, Silex Insight
  • Fabian Schuiki - PhD Student, ETH Zurich
  • Ali Lemus - Director of Research, Galileo University
  • Mark Corbin - Embedded Operating Systems Lead, Embecosm
  • Charlie Su - CTO and SVP, Andes Technology Corporation
  • Aravind Prakash - Assistant Professor, Binghamton University
  • Nathan Pemberton - Graduate Student Researcher, UC Berkeley
  • Olof Kindgren - Senior Digital Design Engineer, Qamcom Research & Technology
  • Cesare Garlati - Co-Founder, Hex Five Security
  • Nicolae Tusinchi - Product Specialist Design Verification, OneSpin Solutions
  • Simon Davidmann - CEO, Imperas
  • Vladimir Herdt - Ph.D. Student, University of Bremen
  • Francesco Menichelli - Assistant Professor, Sapienza University of Rome
  • Jhalak Sharma - MS by Research VLSI, IIT Bangalore
  • Ben Marshall - Research Associate, SCARV Project, University of Bristol
  • Tobias Kaiser - Research Assistant, TU Berlin, Mixed Signal Circuit Design
  • Kurt Keville - Researcher, MIT
  • Sandro Pinto - Professor, Universidade do Minho
  • Christos Kotselidis - Assistant Professor, The University of Manchester
  • Security enclave based on RISC-V technology, Pieter Willem, Silex Insight
  • Kosmodrom: Energy Efficient Ariane Cores with Transprecision FPU in 22nm, FabianSchuiki, ETH Zurich
  • V-Sim: An Open Source and Education-Oriented RISC-V Assembler and Runtime Simulator, Ali Lemus, Galileo University
  • Optimized Softfloat Routines for RISC-V, MarkCorbin, Embecosm
  • Enabling Domain-Specific Architecture from Custom Instructions to Multiprocessor Architectures, Charlie Su, Andes Technology
  • Analyzing RISCV Binaries, Aravind Prakash, Binghamton University
  • FireMarshal: A New Workload Management System for FireSim, Nathan Pemberton, UC Berkeley
  • FuseSoC - Cores never been so much fun, Olof Kindgren, Qamcom Research & Technology
  • RISC-V Security: A New Zero-Trust Model Entirely Based on Free and Open Standards, Cesare Garlati, HexFive Security
  • Unbounded Formal Verification of RISC V CSRs with Interval Property Checking, Nicolae Tusinschi, OneSpin Solutions
  • RISC-V Verification Techniques for Implementations and Custom Extensions, Simon Davidmann, Imperas Software
  • RISC-V based Multi-Core Virtual Prototype: An Extensible and Configurable Platform for Modeling and Verification, Vladimir Herdt, University of Bremen
  • The First Porting of Linux OS Support for Approximate Memory Management on RISC-V, Francesco Menichelli, Sapienza University of Rome
  • The Industry-First Secure IoT Stack for RISC-V: a Research Project, Sandro Pinto and Jose Martins, Universidade do Minho
  • Fault Injection Framework to Study the Soft Error Resilience of RISC-V cores on the FPGA, Jhalak Sharma, IIIT Bangalore
  • XCrypto: a general purpose cryptographic ISE for RISC-V, Ben Marshall, University of Bristol
  • An EnergyBenchmarking Framework for RISC-V Systems-On-Chip, Tobias Kaiser, TU Berlin, Mixed Signal Circuit Design
  • RISC-V HPC Benchmarks, Kurt Keville, MIT
  • RISC-V code generation in MaxineVM, an Educational Use Case, Christos Kotselidis, The University of Manchester
14:50 - 15:20 30 mins
Networking Break
15:20 - 15:45 25 mins
Info
Gold Sponsor
PolarFire SoC: A Secure, Low Latency Heterogeneous Compute Platform for the Edge
  • Ted Speers - Board member | Head of Product Architecture and Planning, Technical Fellow, RISC-V Foundation | Microchip Technology
15:45 - 16:00 15 mins
Info
Community Building
CHIPS Alliance – An Open Hardware Group
  • Yunsup Lee - Vice Chair, Program Committee | CTO, SiFive

CHIPS Alliance is a 501(c)6 nonprofit organization, under the Linux Foundation. The mission is to provide a reputable home for an open-source ecosystem to enable the design of faster, lower cost, more flexible IP for FPGAs and chips. The purpose of CHIPS Alliance is to 1) create an independent legal entity to which companies and individuals can donate resources and collaboratively develop open-source RTL for RISC-V based SoCs, complex peripherals and related IP for FPGAs and chip design, 2) establish a curation process that produces successful projects used in real, commercial SoC design that reduce the cost of development, 3) supply approved projects with infrastructure resources, processes, and management oversight to maintain high-quality, open-source hardware output while supporting a culture of auto governing projects, and 4) provide the SoC user community with free access to high-quality, open-source hardware -- free from patent disputes. CHIPS Alliance currently consists of Google, Western Digital, SiFive, Esperanto and Antmicro.



16:00 - 16:15 15 mins
Info
Community Building
PULP Platform: What's next?
  • Frank Gürkaynak - Senior Scientist, ETH Zurich

The Parallel Ultra Low Power (PULP) Platform started as a research project by ETH Zurich and the University of Bologna in 2013 with the goal of developing high quality, openly available platforms that achieve the highest energy efficiency. The project soon embraced the RISC-V ISA and went on to develop efficient implementations of both 32 and 64bit RISC-V  cores in SystemVerilog and made these cores available using Solderpad, a  permissive open source license. The ETHZ group designed and tested more than 25 ASICs in this short time, and PULP systems were actively used or evaluated by major industry players such as NXP, Google, and IBM. In this talk, we will share our vision for the next 5 years of PULP development and the global momentum driving the PULP Platform ecosystem.

16:15 - 16:30 15 mins
Info
RISC-V Projects
Bridging the Gap in the RISC-V Memory Models
  • Stefanos Kaxiras - Professor, Uppsala University and Eta Scale AB
  • Alberto Ros - Professor, University of Murcia and Eta Scale AB

We present our recent work, published in ISCA 17 (an IEEE Micro Top Picks) and ISCA 18, as well as new unpublished work (under submission to ISCA 19) that reshapes the way we think of memory consistency models. In particular, we will explain how we can bridge the"gap" between Total Store Order (TSO) and Release Consistency (RC) (or similar weak memory models such as RVWMO) so that they exhibit comparable degrees of load and store reordering (hence similar performance) no matter what the underlying microarchitecture. Our approaches mainly modify the behavior of the cache coherence, requiring only minor changes in the pipeline and store buffer to support the same liberal dynamic reordering across memory models. The implication for RISC- V architectures is a unified behavior across its two defined memory models (RVWMO and Ztso), in many cases providing increased instruction reordering that can in some cases even exceed that of the RC model.

16:30 - 16:45 15 mins
Info
RISC-V Projects
The first space-qualified Klessydra RISCV microcontroller to be launched on a satellite
  • Mauro Olivieri - Associate Professor, Sapienza University of Rome, Visiting Researcher at Barcelona Supercomputing Center
  • Luigi Blasi - Ph.D. Candidatie, Sapienza University of Rome
  • Francesco Vigli - Digital Hardware Designer, Sapienza University of Rome

The presentation addresses the space-qualified branch of the Pulpino-compatible Klessydra family of cores, which was preliminarily introduced in a poster presentation at the June 2018 RISC-V Workshop. The project originated from the challenge of having the first RISC-V processor core launched on a space satellite by the end of 2019 within a European Space Agency initiative.  Space-qualified processors face the space radiation problem, causing several types of effects on digital integrated circuits. Effects range from cumulative degradation (Total Ionizing Dose) to bit flip in combinational cells (Single-Event-Transient) and in sequential cells (Single Event Upset), up to reversible malfunctions requiring system reset (Single-Event-Functional-Interruption).  A number of countermeasures exist to these effects, such as shields, rad-hard fabrication technology, multi-processor redundancy, multi-core redundancy, within-core microarchitecture redundancy, along with software support. Recently, due to the high cost of specialized technologies and the growing demand for small satellite applications, techniques favoring the use of COTS components are increasingly favored. Furthermore, the possibility of soft-cores implemented in FPGAs opens the way to additional instruments for adapting the system to harsh environmental effects. The target satellite will employ an RV32I Pulpino as payload on-board computer for data analysis. In order to define the adopted design solution, an extensive set of fault tolerance techniques, explicitly tailored to the RISC-V architecture, were implemented and evaluated by RTL fault-injection. The techniques included partial and full Triple-Modular-Redundancy on threads’ register files and CSRs, pipeline doubling with lockstep execution,  checkpoint setting, and status recovery, memory ECC protection, delayed shadow thread with the single and double pipeline. Many techniques leverage the inherent multi-threaded execution of the Klessydra microarchitecture. Software control of the underlying architecture is achieved through extended CSRs without instruction extensions. The baseline final design features a hybrid redundancy scheme, with one TMR-enhanced hart and two replicated harts implementing checkpoint/recover mechanism, as well as a windowed watchdog timer. Yet, the distinctive characteristic of the core is the design-for-configurability approach, offering parameterized redundancy to the programmer. Not only the software application can be uploaded to the satellite computer but also the hardware microarchitecture can be partially adapted from earth to the specific effects experienced during the mission. The space-qualified Pulpino-Klessydra RISC-V platform prototyped on a 4cmx3cm TE0714 board is expected to fly in a sun-synchronous Low-Earth-Orbit PocketQube satellite, before the end of this year.

16:45 - 17:00 15 mins
Info
RISC-V Projects
What You Simulate Is What You Synthesize: Design of a RISC-V Core from C++ Specifications
  • Simon Rokicki - Research Engineer, INRIA
  • Olivier Sentieys - Professor, INRIA

Designing the hardware of a processor core as well as its verification flow from a single high-level specification would provide great advantages in terms of productivity and maintainability. In this work, we highlight the gain of starting from a unique synthesis and simulation C++ model to design a RISC-V core. The specification code is used to generate both the hardware target design through High-Level Synthesis as well as a fast and accurate simulator of the latter through software compilation.  The object-oriented nature of C++ greatly improves the readability and flexibility of the design description compared to classical HDL-based implementations.  The processor model can easily be modified, expanded and verified using standard software development methodologies.  The main challenge is to deal with C++ based synthesizable specifications of core and non-core components, cache memory hierarchy, and synchronization. In particular, the research question is how to specify such parallel computing pipelines with high-level synthesis technology and to demonstrate that there is a potential high gain in design time without jeopardizing performance and cost. Our experiments demonstrate that the core frequency and area of the generated hardware are comparable to existing implementations.

17:00 - 17:10 10 mins
Info
Workgroup Updates
Better Living Through Bit Manipulation: Higher Performance at Lower Power
  • Ken Dockser - Senior Director of Technology, Corporate R&D, Qualcomm

The Bit Manipulation (BitManip) Extensions comprise a small set of instructions that expand the RISC-V base instruction sets and allow common routines to be executed with fewer instructions. The BitManip specification includes two sets of proposed extensions; a base instruction that includes the most commonly used bit manipulation operations, and an extended instructions that add larger, more complex functionally for those who need it.

This talk will cover the two sets of extensions, going over the functional categories and the individual instructions. The intention is to provide enough information for the larger RISC-V community to understand what is currently included in specification so that individuals can provide feedback to the committee on additional bit-wise operations that are needed but are absent from our proposal.

17:10 - 17:20 10 mins
Info
Workgroup Updates
Status Update of RISC-V P Extension Task Group
  • Chuanhua Chang - Senior director of RD/Architecture Division, Andes Technology

The RISC-V P (DSP) extension task group is formed in August 2018. The chair of the task group is Chuan-Hua Chang from Andes Technology. The co-chair of the task group is Eric Flamand from GreenWaves Technologies. The charter of the P extension task group is as follows:  Define and ratify Packed-SIMD DSP extension instructions operating on XLEN-bit integer registers for embedded RISC-V processors. The TG will also define compiler intrinsic functions that can be directly used in high-level programming languages.  The scope of XLEN is expected to be 32, 64, and 128.  The task group will use AndeStarâ„¢ V3 DSP ISA extension and Pulp DSP ISA extension as references for defining the P ISA extension. Both ISA extensions have been supported by gcc compiler and have been implemented in several silicon chips.  The proposed instructions have been documented in a spreadsheet under the review of the task group participants.  This talk will be focused on reporting the progress and the current status of the P extension task group on designing the extension and the issues discussed and determined by the task group participants. Some DSP ISAs comparison and usage analysis will be given in the talk. And more performance data on general DSP functions and audio/speech applications will be given as well to help determine the usefulness of the proposed instructions.

17:20 - 17:30 10 mins
Info
Workgroup Updates
Crypto Currently: The state of the Cryptographic Extensions and the challenges we face
  • Ken Dockser - Senior Director of Technology, Corporate R&D, Qualcomm

The Cryptographic Extensions build upon the RISC-V Vector extensions, using the same vector registers and access rules. These new instructions will accelerate the execution of commonly utilized cryptographic and secure-hash algorithms.

The initial cryptographic extensions are aimed at the most common algorithms including AES encryption and decryption, and SHA-2. The base crypto extensions are RISC-like round-based instructions, similar to what is offered by other leading architectures. The extended extensions are more CISC-like and are all-rounds based; these are more complex to implement but are convenient for those looking to thwart power and EM side channel leaking of keys.


This talk will educate the community on some of the issues the task group is confronting so that potential implementers and coders will be able to provide feedback on which approach will work best for them. One such issue is how to support cryptographic algorithms --- which commonly require data and keys in chunks of 128-bits, 256-bits and wider --- in embedded vector implementations comprised of narrow (e.g., 32 bit) register files. Another issue is how to support more cryptographic algorithms that can fit in the limited 32-bit opcode space. Current ideas range from context-based approaches where the meaning of a cryptographic instruction (e.g., the algorithm to be implemented) is taken from the contents of a register to a wider-instruction approach where the less common algorithms are specified with 48-bit instruction encoding. Some of the pros and cons of each approach will be presented.

17:30 - 17:40 10 mins
Info
Workgroup Updates
Toward High-Quality RISC-V Vector Extension
  • Dmitry Gusev - VP of Engineering, Syntacore
  • Pavel Smirnov - Lead Engineer, Syntacore

Vector calculations are known and a proven path to efficiency for a great variety of applications including linear algebra, machine learning, signal processing, and many other computational domains. In this session, we present results of the study, devoted to the analysis of the published RISC-V vector ISA extension draft. During this exercise, authors reviewed a variety of vectorizable applications and mapped these to the vector ISA, using vector ISA simulator and basic toolchain prototype. We assess the applicability of the vector extension draft and analyze effectiveness and flexibility of the proposed instruction basis for a variety of common usage patterns, including sorting and search algorithms, BLAS routines, FFT, digital filtering and number of others. The paper both demonstrates the strengths of the proposed vector extension ISA when applied to the practical topics and also highlights few potential limitations. We propose several possible directions to mitigate these and review several corner cases that require additional attention. We compare the performance of different algorithms implementations using RISC-V vector extension simulator and present numerical results of the experiments. In conclusion, we propose possible changes to the specification and assess its usability from a programmer's point of view.

17:40 - 17:50 10 mins
Info
Workgroup Updates
Vector Extension 0.7
  • Krste Asanovic - Professor / Chief Architect, UC Berkeley | SiFive

The vector extensions have reached a major milestone with the release of version 0.7, which is intended for widespread implementation and comment.

18:00 - 20:00 120 mins
Networking Reception
08:00 - 09:00

Registration & Networking

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10:35 - 11:05

Networking Break

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12:30 - 13:30

Networking Lunch & Table Tops Visit

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14:50 - 15:20

Networking Break

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18:00 - 20:00

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