RISC-V Workshop, Zurich is part of the Informa Tech Division of Informa PLC

This site is operated by a business or businesses owned by Informa PLC and all copyright resides with them. Informa PLC's registered office is 5 Howick Place, London SW1P 1WG. Registered in England and Wales. Number 3099067.

Informa
June 12, 2019
Show Filter
08:00 - 09:00 60 mins
Networking & Registration
09:00 - 09:25 25 mins
Info
Software
RISC-V Software State of the Union
  • Palmer Dabbelt - Engineer, SiFive

In this talk, I'll present the state of the embedded and Linux RISC-V software ecosystem.

09:25 - 09:50 25 mins
Info
Software
Embench TM: A Free Benchmark Suite for Embedded Computing from an Academic-Industry Cooperative (Towards the Long Overdue and Deserved Demise of Dhrystone)
  • David Patterson - Vice Chair, RISC-V Foundation
  • Jeremy Bennett - Chief Executive, Embecosm

The embedded industry (still) relies on synthetic programs to advertise performance: Dhrystone and CoreMark. Textbooks have labeled synthetic programs as inappropriate for benchmarking for many reasons since 1990.  They force developers to choose between making actually superior processors and compilers versus getting higher Dhrystone and CoreMark scores that affect marketing and sales.   Ideally, improved technology and higher benchmark scores align, which is the aim of Embench (for Embedded Benchmark). We think synthetic programs are still widely quoted in part because they are easily ported and cost nothing to use, which is also the goals for Embench.  A group of interested parties from academia and industry started meeting in January 2019 with the goal of quickly developing the foundation for a good benchmark suite for embedded computers. The goal was to keep the group small initially to be able to have extensive discussions to get to a good starting point and then invite others to join to improve the benchmark.  We plan to follow “Agile Benchmark Development” by bringing out an initial 0.5 version for evaluation and feedback.   The Embench Version 0.5 suite has ≈20 programs. They do little or no floating point computation, but some are branch intensive, some memory intensive, and some integer compute intensive. Like SPEC, the single performance number that people will promote is the geometric mean of performance relative to a reference platform of the ≈20 programs plus the multiplicative standard deviation to indicate the significance of differences between processors. We initially aim to evaluate microcontrollers that support ≤64KiB of code and read-only data -- which would typically be stored in Flash or ROM and 16KiB of data.  Novel features of Embench include reporting code size as well as program performance and to measure interrupt latency and context switching along. These novel features play an important role in embedded computing but have not yet appeared in embedded benchmarks.   Regarding the more traditional challenge of selecting programs for the suite, the good news is that several universities attempted embedded benchmark suites previously -- such as MiBench from the University of Michigan and BEEBS from the University of Bristol -- so we have a large set of mature, publicly available, and portable programs to build upon.  If Embench succeeds, then embedded computing can return synthetic benchmarks to the dustbin of history, which is where they have long belonged.

09:50 - 10:15 25 mins
Info
Software
Open Source Compiler Tool Chains and Operating Systems for RISC-V
  • Jeremy Bennett - Chief Executive, Embecosm
  • Mark Corbin - Embedded Operating Systems Lead, Embecosm

The first part of this presentation will survey the current status for free and open source compiler toolchains for RISC-V. The two major toolchains, GNU and LLVM will be examined in detail as well as less widely known tools such as the Plan 9 C compiler. The talk will consider all components of the toolchains - low-level binary utilities - assemblers - linkers - compilers - emulation, C and C++ libraries - debuggers, remote debugging and simulators For each component we will look at the functionality currently available, including exploring support for languages other than C and C++. Most of these components incorporate standard test suites and the talk will look at the current status of those tests. We'll also report on the performance of each toolchain, looking at generated code size and execution speed, using the new embedded benchmark suite.

In the second part of this talk, we look at the growth in open source operating system support for the RISC-V architecture. RISC-V is supported by a range of operating systems from real-time kernels for IoT applications to fully-featured distributions for high-end systems or servers. We shall look at RISC-V support for mainstream Linux distributions (Debian, Fedora, Gentoo, and openSUSE), Embedded Linux distributions (Buildroot, OpenEmbedded/Yocto, and OpenWrt), BSD variants (FreeBSD and NetBSD), real-time operating systems (Apache Mynewt, FreeRTOS, and Zephyr) and the distributed operating system, Plan 9.

10:15 - 10:30 15 mins
Info
Software
Enabling RISC-V Development with QEMU
  • Alistair Francis - Principal Engineer, Western Digital

With RISC-V software becoming easier to use and more commonplace there is a lot of interest in development and testing software projects on RISC-V systems. As there is still limited RISC-V hardware options, especially when it comes to booting Linux, this can be difficult to do. This presentation will discuss why QEMU can be used instead of hardware to develop, test and debug RISC-V software. It will cover how QEMU works and how it can be used for RISC-V ecosystem enablement. This will include steps and a demonstration on getting started with QEMU. It will also cover useful tricks to aid in debugging guest application problems. Some of which were used to develop and debug openSBI. The talk will also go over what does and doesn't work today and what we are planning in the future

10:30 - 11:00 30 mins
Software
Networking Break
11:00 - 11:25 25 mins
Info
Software
Building Better Soft RISC-V IP Cores through Mi-V verification and compliance Testing
  • Stuart Hoad - Senior Principal Architect, Microchip Technology
11:25 - 11:50 25 mins
Info
Software
Developing with FreeRTOS and RISC-V
  • Richard Barry - Principal, Software Dev, AWS

The open source (now MIT licensed) FreeRTOS kernel has helped embedded developers manage the complexity of their microcontroller designs for 15 years -- during which time FreeRTOS has gained a reputation for reliability, ease of use, and responsive support. Under the stewardship of Amazon Web Services (AWS), the FreeRTOS project has expanded to include MIT-licensed security and connectivity libraries under Amazon FreeRTOS. In February, AWS announced official upstream support for RISC-V in the FreeRTOS kernel, enabling developers to create new or migrate existing FreeRTOS-based applications on RISC-V microcontrollers using fully-tested and supported FreeRTOS kernel libraries. In this talk, Richard Barry, the founder of the FreeRTOS project, will demonstrate how the kernel's extensible architectures enable FreeRTOS to run on a range of RISC-V implementations, and how you can integrate Amazon FreeRTOS libraries to give your devices OTA capabilities and connectivity over BLE and Wi-Fi.

11:50 - 12:05 15 mins
Info
Software
Enable RISC-V capability in cloud computing
  • Zhipeng Huang - Principle Engineer, Huawei

With cloud computing becomes ever more dominant, it is vital to deliver RISC-V capability through the cloud, either a "RISC-V as a Service" via public cloud or RISC-V resource provisioning via the private cloud.  In this talk, we will introduce some open source projects we are leading which offers management framework for heterogeneous computing resources for OpenStack and Kubernetes. We will further discuss how to better support RISC-V on the cloud via development of drivers of RISC-V chips for these cloud management frameworks. We will also share our ongoing discussion and collaboration with the FireSIM team as an example.

12:05 - 13:05 60 mins
Networking Lunch and Table Top Visits
13:05 - 13:20 15 mins
Info
Tools, Debug, Verification
SweRV (RISC-V) Debug, Trace and On-chip Analytics for SOC
  • Sesibhushana Rao Bommana - Technologist, Western Digital
  • Mukesh Panda - Technologist, Western Digital

SweRV Debug, Trace and On-chip Analytics for SOCs As SoC designs become ever more complex with levels of system integration increasing, multifunctional, multicore SoC are now the fastest growing section of ASIC/ASSP design. This paper abstracts the architecture of SweRV (RISC-V) Debug, Trace and On-chip Analytics for SOC as a whole. Considering the SweRV developed based on RISC-V specification, which has great market potential in various fields of applications. Solid Debug and Trace along with SOC Analytics are very important.    

Problem statement: A system on chip (SOC) is an Integrated Circuit (IC) that integrates various components of a computer or other electronic system into a single chip.  There will be many building blocks in the system, architects stitch them together in order to extract the required performance and ensure that the desired applications can run. Currently, many SOCs are does not have an effective insight into SOC related to its performance. This was a problem as the system designer won't aware accurately whether the SOC meets the performance requirements intended and won't be able to fix the issues prior to release the SOC into the hands of the customers.  Also, the designer won't be able to compare his own products against the products from 3rd party vendors. Performance tuning is the highly important factor in the Storage SOCs.  On-chip Analytics and tuning are required at every step in the development phase of the SoC. Key performance metrics need to be continually checked and updated during the lifecycle of the development phase of an SoC. Moreover, SoC designs are becoming extremely complex that the complete performance validation at design time is almost impossible. Performance needs to be monitored at run-time that enables the application on the given hardware platform to improve the QOS. Current debugging and trace tools will not be capable of providing insight in triggering and visualizing the SOC.  Existing Approach Existing approach vastly depends on the trace tools that are CPU centric. Minimal on-lab debug with a poor system-level test, no in-life monitors. The data generated using the existing approach is partial and won't beneficial full extent that results in months of debug time and underperformed product delivery to customers.   In complex systems understanding the program behavior is not easy. Surprisingly, software sometimes does not behave as expected. This may be due to a number of factors, for example, interactions with other cores software, peripherals, real-time events, poor implementation or some combination of all of the above. Using a debugger is not always possible as real-time behavior is affected. Providing visibility of program execution is important. Understanding the program behavior in the field at real-time is needed.  

 Proposed Approach: An efficient Branch Trace scheme provides visibility of program execution. Couple this with a Holistic non-intrusive monitoring infrastructure provides the means of understanding complete SoC behavior and various on-chip performance metrics. It is possible to trigger on various signals within the SOC, CPU states and get the snapshot of the entire SOC to transfer the real-time trace data to the External IDE for further analysis. A customer can develop an AI engine to process the data on real-time for detection of issues in advance. External IDE can configure and control the debug and monitoring hardware using the JTAG interface. A user can choose either the JTAG interface or high-speed bus like USB/SerDes to debug or to transfer the trace data to IDE for real-time analysis.  Below the advantages of the proposal. 

  • Full SoC visibility, HW & SW 
  • Support all architectures: Freedom of IP selection
  • Real-time & non-intrusive does not impact/degrade system performance •\tAdvanced analytics & forensics 
  • Power/Performance optimization 
  • Smart monitoring and "in life" analytics  
  • Supports Functional Safety 
  • Supports Bare Metal Security
  • High-speed debug: USB or SerDes Spending a small amount of die area to accelerate TTM and improve lifetime profit with improved performance and reduced power.

Summary:  On-Chip Analytics is a powerful visualization tool for viewing performance metrics inside the SOC, both in real time and for post-processing. With it, we can examine performance data in a graph, histogram, report or waveform. It can also check for the protocol compliance of any interface connected.  Having Combined Debug and System monitoring in the SOC will give in-depth insight to the system designers and analyze the performance bottlenecks of the target system in an efficient manner. Performance tracking is all about measuring various metrics. Bus transactions are the most interesting to observe and are not observable from outer pins, which prompts the inclusion of on-chip trackers. By combining the Debug and the Performance Monitors will enable the user to get a command over the debugging vs the longer debugging cycles associated with corner cases.

13:20 - 13:35 15 mins
Info
Tools, Debug, Verification
TestRIG: Using RVFI-DII to eliminate the "Test gap" between specification and implementation
  • Jonathan Woodruff - Research Associate, University of Cambridge

We have built a framework for model-based testing of RISC-V implementations which can check test equivalence between implementation and specification, or between implementations. This framework, Test using Random Instruction Generation (TestRIG), uses an extension of the RISC-V Formal Interface (RVFI), a verbose trace port, and adds Direct Instruction Injection (DII). A RISC-V implementation or model with RVFI-DII support can accept instructions directly from an external port, bypassing the instruction cache, and provide a detailed trace of state update.  A TestRIG verification engine can then test equivalence between implementations or models that support RVFI-DII by generating sequences of instructions and comparing traces.

13:35 - 13:50 15 mins
Info
Tools, Debug, Verification
Formal Verification of PULPino and other RISC-V SoCs
  • Nicolae Tusinchi - Product Specialist Design Verification, OneSpin Solutions
  • Sven Beyer - Product Manager Design Verification, OneSpin Solutions

RISC-V SoCs integrate multiple RISC-V cores, on-chip bus fabric, peripherals, and I/O interfaces. Cores and other modules may be developed in-house, licensed from third-party IP providers, or leveraged from open-source projects. A rigorous, efficient, and independent functional verification platform is crucial to provide evidence that the SoC implementation is correct and does not include unintended or malicious functions. The work presented in this talk is part of a wider project to develop a comprehensive RISC-V integrity verification solution. The project covers not only integrity of core implementations, through a SystemVerilog formalization of the ISA, but also many aspects of a complete RISC-V SoC. This talk focuses on the application of formal applications and assertion-based verification IPs (ABVIPs) to detect corner-case bugs and unintended functions in the hardware's RTL model. These methods require low engineering effort and limited formal expertise. We present experiences and results from the application to the PULPino SoC. We also report potential functional bugs identified by the FPU ABVIP, which includes an IEEE754-compliant model, the APB protocol ABVIP, and auto checks. Additional investigation is ongoing to determine the exact nature of these issues. Final results will be presented at the Zurich workshop.

13:50 - 14:05 15 mins
Info
Tools, Debug, Verification
Ada & PolarFire SoC, a software and hardware alloy for Safety & Security
  • Fabien Chouteau - Senior Director of Engineering, AdaCore
  • Pierre Selwan - System Architect, Microsemi, a Microchip company

Domains such as space, avionics or automotive are in need of software that behaves as expected, in a deterministic and testable way. This can only be achieved when combining strong software development tools and methodologies with deterministic and safety-aware hardware. This talk will present how the RISC-V platform developed by Microchip, together with the Ada/SPARK language and Ravenscar real-time kernel can provide an optimal environment to achieve this objective. PolarFire SoC from Microchip provides an SoC FPGA platform augmented with a hardened multicore RISC-V Microprocessor subsystem. Microchip's FPGA technology is unique in that the FPGA configuration cells are immune to Single Event Upsets. The Microprocessor subsystem implements SECDED on all memories, and working with their IP provider SiFive were able to achieve determinism in the five CPUs and in the L2 memory subsystem. Software running on the Microprocessor subsystem can use the Ada Ravenscar real-time kernel, which will add to the list of enforced properties:  absence of deadlocks, the absence of priority inversions, schedulability, and determinism. The last component to include in the mix is the Ada/SPARK programming language, which will be able to demonstrate safety characteristics in the software being written, from simple things such as the absence of memory errors (buffer overflow) to functional correctness, using advanced static analysis technologies know as a formal proof.

14:05 - 14:20 15 mins
Info
Tools, Debug, Verification
Building Secure Systems using RISC-V and Rust
  • Arun Thomas - Systems Researcher, Draper Labs

How should one build a secure computer system in the 21st Century?  In this talk, I argue the RISC-V architecture and the Rust systems programming language are two critical building blocks for secure systems of the future. Together, they provide a strong foundation for building flexible, secure, reliable computer systems.  I will give an introduction to the Rust language and an overview of the Rust ecosystem. I will also discuss the status of Rust on RISC-V and walk through the process of developing Rust for RISC-V targets. This talk is meant to be a quick start guide for those new to Rust and RISC-V development.

14:20 - 14:50 30 mins
Info
Posters
60 second Poster Preview Sessions
  • Simon Davidmann - CEO, Imperas
  • Mary Bennett - Software Engineer Intern, University of Surrey/ Embecosm
  • Matheus Cavalcante - PhD Student, ETH Zurich
  • Michael Gielda - VP Business Development, Antmicro
  • Mauro Olivieri - Associate Professor, Sapienza University of Rome, Visiting Researcher at Barcelona Supercomputing Center
  • Nanda Pallari - Senior Manager of Flash Product Group, Western Digital
  • Antti Lukats - CTO, Trenz Electronic GmbH
  • Alexander Kamkin - Leading Researcher, ISP RAS
  • Noureddine Ait Said - Ph.D. Student, TIMA Laboratory (Grenoble INP, UGA, CNRS)
  • Manpreet Jaswal - Ph.D Student, International Institute of Information Technology, Bangalore
  • Spoorthi Rao - M.S. Scholar, IIT Bangalore
  • Subir Kumar Roy - Professor, IIT Bangalore
  • Simon Rokicki - Research Engineer, INRIA
  • Michael Gautschi - Senior Digital Design Engineer, Advanced Circuit Pursuit AG
  • Florian Glaser - Associate Researcher, ETH Zurich
  • Ali Lemus - Director of Research, Galileo University
  • Onno Martens - Team Leader IC Design, TRINAMIC Motion Control GmbH & Co. KG
  • Tiago Jost - Ph.D. Candidate, ENS Paris and CEA
  • Abdallah Cheikh - Ph.D. student in ICT, Sapienza University of Rome
  • Stefano Sordillo - Master's Student, Sapienza University of Rome
  • RISC-V Processor Models for Software Bring Up and Hardware-Software Co-Verification for multicore SoC designs, Simon Davidmann, Imperas Software
  • Using SAIL to Generate GNU Assembler/Disassembler and Simulator for RISC-V, Mary Bennett, Embcosm
  • ARA v2: Design of a High-Performance 64-bit RISC-V Vector Coprocessor, Matheus Cavalcante, ETH Zurich
  • Design Cycle Acceleration for Hardware/Software Co-Design with Renode, Michael Gielda, Antmicro
  • The first Klessydra RISC-V Core Exploiting Configurable Vector Acceleration for High-Performance Edge-Computing, Mauro Olivieri, Abdallah Cheikh, and Stefano Sordillo, Sapienza University of Rome
  • SweRVing into a RiscFree -- IDE lane with an Eclipse-based Toolchain Supporting Heterogeneous Cores Nanda Kumar Pallari, Western Digital
  • RISC-V "micro-SoC" Implementation on Different  FPGA Platform, Antti Lukats, Trenz Electronic GmbH
  • Memory Management in MicroTESK TPG for RISC-V, Alexander Kamkin, ISP RAS
  • Teaching Hardware/Software Codesign Using Rocket Chip, Noureddine Ait Said, TIMA Laboratory (Grenoble INP, UGA, CNRS)
  • Performance Enhancement of RISC-V cores through Value Prediction based on Dynamic Data Flow Analysis, Manpreet Kaur Jaswal, International Institute of Information Technology, Bangalore
  • Low Power High-Performance Decimal Floating Point Co-Processor for RISC-V, Spoorthi Rao and Subir K. Roy, International Institute of Information Technology, Bangalore
  • Hybrid-DBT: Hardware-Accelerated Dynamic Binary Translation Targeting VLIW Processors, Simon Rokicki, INRIA
  • A Dual-Mode NB-IoT and EC-GSM Multi-Core RISC-V RF-SoC with Tightly-Coupled Accelerators, Michael Gautschi, Advanced Circuit Pursuit AG
  • A RISC-V Based Multi-Functional Platform for Miniaturised Medical Instrumentation, Florian Glaser, ETH Zurich
  • V-Sim: An Education-Oriented RISC-V Assembler Linker and Runtime Simulator, Ali Lemus, Galileo University
  • The Soul of a New SoC: Hands-On Experience With Embedding a RISC-V Core, Onno Martens, TRINAMIC Motion Control GmbH & Co. 
  • Variable Precision Capabilities in RISC-V Processors, Tiago Trevisan Jost, CEA, LETI, Univ. Grenoble Alpes
14:50 - 15:20 30 mins
Networking Break
15:20 - 15:45 25 mins
Info
Security
An open-source API proposal for a multi-domain RISC-V Trusted Execution Environment
  • Cesare Garlati - Co-Founder, Hex Five Security

Trusted Execution Environments (TEEs) have historically suffered from an excess of complexity and overhead that has constrained their adoption to regulated markets that force a TEE upon OEMs.  With RISC-V, the basic security hooks for a TEE are already in the ISA, however, that is missing is a simple, standard API that TEE developers and application developers alike can develop upon. In this presentation, Cesare Garlati will present the development history of and present implementation of the open source MultiZone Security API as a proposed standard for adoption in the RISC-V community and beyond.  It presents a minimalist API structure enabling an extremely thin formally verifiable TEE micro kernel and services which can be layered into each domain as required by the application.  Unlike TEE API standards from Global Platforms and other standards groups, this API is presented as an implemented C .h file can that be immediately adopted and standardized by TEE developers and application developers alike.

15:45 - 16:00 15 mins
Info
Security
Protecting RISC-V Processors against Physical Attacks
  • Mario Werner - Ph.D. Candidate & Teaching Assistant, Graz University of Technology
  • Robert Schilling - Ph.D. Candidate & Teaching Assistant, Graz University of Technology

RISC-V is well-suited for a wide variety of applications, which ranges from simple microcontrollers to high-performance CPUs. As an increasing number of commercial vendors now adopt the architecture in their products, its security aspects are becoming a significant concern. For embedded applications, one of the main security risks are attackers with direct physical access to the microchip. These physical attackers can perform highly powerful attacks that span from memory probing to power analysis up to fault injection and analysis. In this talk, we give an overview of the capabilities of attackers with direct physical device access, common threat models and attack vectors, and possible countermeasures. We present our current approaches to secure RISC-V processors against fault injection attacks on the microchip itself. First, we show how to protect the control-flow against fault attacks by using an encrypted instruction stream and decrypting it on-the-fly in a newly added pipeline stage between the processor's fetch and decode unit. Second, we show how to protect conditional branches against fault injection by adding redundancy to the comparison operation and entangling the comparison result with the encrypted instruction stream. Finally, we show an approach to protect all pointers and memory accesses from tampering.

16:00 - 16:15 15 mins
Info
Security
A Security Policy Definition Language, Semantics, and Open Source Tools
  • Greg Sullivan - Chief Scientist, Dover Microsystems
  • Chris Casinghino - Principal Member of the Technical Staff, Draper

We present a domain-specific language for specifying fine-grained security policies. Further, we provide a mapping from the high-level policy language to the RISC-V instruction set. A policy defines the allowed/disallowed runtime behavior of all software running on a RISC-V system. A policy definition consists of rules that check and update metadata for all values (in registers or memory) accessible by the host RISC-V CPU. We will demonstrate how you can specify policies for memory safety, privacy, compartmentalization, and more. The presentation will include ongoing research into formalizing the semantics of the policy language, creating tools for validating policies with respect to higher level specifications, and other analyses, both static and dynamic. The presentation will include demonstrations of open source tools for compiling and evaluating policies, in conjunction with open source RISC-V simulators. We will briefly discuss various hardware-supported mechanisms for directly supporting policy enforcement, as well as how hardware mechanisms such as physical memory protection, shadow stacks, and other proposals can be used to provide elements of a system-wide security policy.

16:15 - 16:30 15 mins
Info
Security
An Intrinsically Secure RISC V processor
  • Olivier Savry - Researcher, CEA

Cyber attacks on CPS or IoT are now making the headlines more and more often. There is much evidence to suggest that this growth is no longer linear but exponential. The slightest vulnerability is exploited and as far as processors are concerned, the very details of the microarchitecture are attacked (e.g. Spectre and meltdown). In our opinion, the main reason for this upsurge is that many products are still being developed without any concern for security. Its knowledge requires expertise that is nowadays rare and expensive. It is therefore highly unlikely that a security expert can be put behind each software developer. To overcome this situation, we have developed the concept of an intrinsically secure processor. It obviously uses the ISA RISC V because the RISC V initiative makes it possible to openly address processor security without the obfuscation that was required in some ISAs and CPU developments and to lower the cost of marketing. The idea is that the developer can compile his program to run it on this type of processor without having to worry about the security of the underlying hardware and of a part of the software. Indeed, in the generated code, each instruction and each data are encrypted and associated with a MAC to ensure authenticity and integrity. In general, Control Flow Integrity (CFI) techniques ensure that the processor follows correctly the Control Flow Graph correctly. We add to this functionality, confidentiality but also data integrity and the possibility to move the ciphered code in memory what any OS using virtual memory like Linux needs. This global approach is totally innovative.

16:30 - 16:45 15 mins
Info
Commercial Offerings
SiFive 7-series RISC-V Core IP Enables Embedded Intelligence
  • Yunsup Lee - Vice Chair, Program Committee | CTO, SiFive

Modern compute workloads require scalable, efficient solutions as more intelligence is moving to edge devices. As the highest performance commercial RISC-V processors, SiFive's E7, S7, and U7 CPU cores brings hard real-time capabilities and unprecedented scalability from 32-bit embedded processors to 64-bit application processors. As with all of SiFive Core IPs, the application processors and real-time processors can be combined coherently in the same compute cluster. In this talk, we will discuss the 7-series and how it can be used in real-time embedded applications.

16:45 - 17:00 15 mins
Info
Commercial Offerings
CloudBEAR RISC-V Processor IP Product Line
  • Alexander Kozlov - CTO, CloudBEAR

We will present RISC-V processor cores for the widest range of applications: from embedded control to Linux high-end. Company's Linux-capable core complexes will be presented including most high-performance mid-range out-of-order application core BI-671, BI-651 complex targeting single-thread performance in power constrained environment and BI-350 tiny Linux core for low-cost IoT applications. In the talk, we will be showcasing cores features and SPEC2006 benchmarks.

17:00 - 17:15 15 mins
Info
Commercial Offerings
Syntacore 64bit RISC-V core IP product line
  • Alexander Redkin - Director, Syntacore
  • Dmitry Gusev - VP of Engineering, Syntacore

We describe the family of the state-of-the-art RISC-V compatible microprocessor core IP developed by Syntacore with a specific focus on details of our 64bit product line and roadmap. SCRx family now includes eight industry-grade cores with comprehensive features, targeted at different applications: from compact SCR1 MCU core, which is one of the first fully open industry-grade RISC-V compatible cores (introduced in 2017) to the high-performance 64bit Linux-capable multicore SCR7. Different cores can now be used together in heterogeneous multicore clusters with atomics and memory coherency. Half of the product line is available as 64bit designs.  The SCRx cores have competitive features and deliver impressive performance at low power already in baseline configurations. On the top, Syntacore provides a one-stop workload-specific processor customization service to enable customer designs differentiation via significant performance and efficiency boost. Industry-standard interfacing options support (AHB, AXI4, ACE) enables seamless integration with existing designs. In the session, we detail cores features, benchmarks and collateral availability.

17:15 - 17:30 15 mins
Info
Commercial Offerings
Configurable LLDB Debuggers for RISC-V
  • Zdenek Prikryl - CTO, Codasip

Codasip has long been a contributor to the LLVM project as LLVM consistently delivers a better quality of results than other open source compiler toolchains. However, while the compiler has been best-in-class for some time, the debugger in the LLVM project (LLDB) has not evolved as quickly leading many vendors to offer a hybrid approach to the tools. Fortunately, recent advancements in the LLDB project have improved its robustness and stability, consequently making it a natural choice to include with the rest of the toolchain. Full support for LLDB in command line mode or as part of an Eclipse-based graphical debug is now part of Codasip’s latest generation of licensable software development tools.   Further, since LLDB is relatively new, it carries less burden of legacy, is easier to extend and reconfigure, and has the advantage of modern libraries and the full power of the Clang expression parser which is especially important in handling complex C expressions.   Codasip Codespace is the industry’s first commercially deployed LLVM toolchain for RISC-V that includes LLDB. It converts debug information into clang types so that it can leverage the clang compiler infrastructure thus allowing the debugger to support the latest C, and C++ language features and runtimes in expressions without having to re-implement any of this functionality. It also leverages the latest version of the DWARF standard that, among the other things, improves support for the latest C/C++ standards.   The presentation will demonstrate how a Codasip configured LLDB debugger can handle non-standard instruction extensions, including disassembly and debug, how LLDB works with Codasip ISS or OpenOCD giving users a powerful new tool for the software debugging on either standard or optimized RISC-V processors.

17:35 - 19:35 120 mins
Info
RISC-V Foundation Members Dinner

RISC-V Foundation Members only.

Join fellow RISC-V Foundation members for networking and light dinner in the Faculty Restaurant to connect before the member meetings begin on June 13.

08:00 - 09:00

Networking & Registration

More
Showing of Streams
12:05 - 13:05

Networking Lunch and Table Top Visits

More
Showing of Streams
Showing of Streams
14:50 - 15:20

Networking Break

More
Showing of Streams
Showing of Streams
17:35 - 19:35
Info

RISC-V Foundation Members Dinner

RISC-V Foundation Members only.

Join fellow RISC-V Foundation members for networking and light dinner in the Faculty Restaurant to connect before the member meetings begin on June 13.

More