RISC-V Workshop, Zurich is part of the Informa Tech Division of Informa PLC

This site is operated by a business or businesses owned by Informa PLC and all copyright resides with them. Informa PLC's registered office is 5 Howick Place, London SW1P 1WG. Registered in England and Wales. Number 3099067.


Olivier Sentieys
Professor at INRIA


I joined the University of Rennes (ENSSAT) and IRISA Laboratory, France, as a full Professor of Electronics Engineering, in 2002. I am leading the CAIRN Research Team common to INRIA Institute (national research institute in computer science) and IRISA Lab., where I am also the head of the “Computer Architecture” department. Since September 2012 I am on secondment at INRIA as a Senior Research Director. My research activities are in the two complementary fields of embedded systems and signal processing. Roughly, I work firstly on the definition of new system-on-chip architectures, especially the paradigm of reconfigurable systems, and their associated CAD tools, and secondly on some aspects of signal processing like finite arithmetic effects, numerical accuracy analysis, and cooperation in mobile systems. I authored or coauthored more than 150 journal publications or peer-reviewed conference papers and hold 5 patents.

Olivier Sentieys's Network

Agenda Sessions

  • What You Simulate Is What You Synthesize: Design of a RISC-V Core from C++ Specifications


Speakers at this event