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June 30, 2018
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8:00am - 8:40am 40 mins
Registration & Networking
8:40am - 8:45am 5 mins
Introducing RISC-V
Welcome Speech 欢迎致辞
more
8:45am - 9:00am 15 mins
Introducing RISC-V
Status of RISC-V Foundation and APAC Group 开场介绍:RISC-V基金会及其APAC小组最新进展
9:00am - 9:25am 25 mins
Commercial/Open Source RISC-V Implementations
Comprehensive RISC-V Solutions for AioT 面向AIoT的基于RISC-V的完整解决方案
  • Charlie Su - CTO and SVP, Andes Technology Corporation
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Andes Technology is the leading Asia-based CPU IP company with over 2.5-billion Andes-Embedded SoCs shipped for diversified applications based on Bare Metal, RTOSes and Linux. Our experience allows us to focus on processors and SW with features important to customers.  In this talk, we will cover RISC-V solutions for AIoT, the combination of AI and IoT. We will introduce RISC-V architecture extensions, performance-efficient RISC-V processors, pre-integrated flexible SoC platform, feature-rich development tools, and IoT software stack, and discuss how they address the low power, acceleration, and security issues in developing AIoT SoCs.

9:25am - 9:50am 25 mins
Commercial/Open Source RISC-V Implementations
The SCR Family of RISC-V Compatible Processor IP 兼容RISC-V的SCR处理器系列IP核
  • Pavel Khabarov - Lead Hardware Engineer, Syntacore
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We present family of the state-of-the-art RISC-V compatible microprocessor core IP developed by Syntacore: from the minimalistic MCU core for the deeply-embedded applications to the 1GHz+ Linux-capable application core with full MMU and SMP support.   As of today, SCR family includes four off-the-shelf cores, targeted primarily at embedded applications: SCR1, SCR3, SCR4 and SCR5.   SCR1 is a compact 32-bit MCU core for deeply embedded applications and accelerator control. It can be configured for a very small area - under 15kGates in a fully-functional configuration, and is open-sourced under the permissive SHL license, which allows commercial use. SCR3 is a high-performance 32-bit MCU core with RV32IMC ISA, privilege modes, MPU and caches.  SCR4 is MCU core with RV32IMCF[D] ISA and high-performance configurable single- or double-precision FPU. SCR5 is efficient mid-range RV[32|64]IMCAFD core with page-based virtual memory, full MMU and SMP configurations (dual- and quad-core), which supports memory coherency and HW atomics.   The SCR cores have competitive features and deliver impressive performance at low power already in the baseline configurations. On the top, Syntacore provides a one-stop workload-specific processor customization service to enable customer designs differentiation via significant performance and efficiency boost. Industry-standard interfacing options support (AHB, AXI4, OCP) enables seamless integration with existing designs.  In the session, we detail cores features, collateral availability and further development roadmap.

9:50am - 10:15am 25 mins
Commercial/Open Source RISC-V Implementations
Introducing the New IP Series by SiFive 来自SiFive的全新IP系列
  • Jack Kang - Vice President of Product Marketing, SiFive
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The RISC-V instruction set architecture is an open standard originally designed for academic computer architecture research that, over the past few years, has been gaining widespread popularity for commercial use. To continue innovation for the growing RISC-V ISA, SiFive has launched the Freedom U500, the industry’s first Linux-capable SoC; and E3 Core IP Series, the industry’s first open-sourced RISC-V SoC for embedded use cases. But it doesn’t stop there. The company’s Core IP is the foundation of the most widely deployed RISC-V cores in the world as these are the lowest risk and easiest path to RISC-V.   At RISC-V Day in Shanghai, Jack will talk about SiFive’s new IP Series (to be announced on June 24).

10:15am - 10:45am 30 mins
Networking Break 茶歇
10:45am - 11:10am 25 mins
Commercial/Open Source RISC-V Implementations
Enhancements to Tools for Automated Generation of RISC-V Processors 增强的RISC-V处理器自动化生成工具
  • Zdenek Prikryl - CTO, Codasip
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The emergence of the RISC-V architecture has given rise to a demand for widely differing microarchitectural implementations, ranging from deeply embedded microcontrollers to DSPs to superscalar processors.   To meet the challenge of addressing so many different operating points it is necessary to abstract the architectural details and to automate the generation and verification of RISC-V microprocessors.   The Codasip approach to delivering RISC-V processor IP is to employ the silicon-proven methodology of the high-level CodAL architecture description language and its suite of tools called Studio to implement various RISC-V microarchitectures  Using Codasip Studio  (an Eclipse-based integrated processor development environment) designers write a high-level description (in CodAL architecture description language) of an processor and then automatically synthesize the design's RTL, testbench, virtual platform models and processor toolchain (C/C++ compiler, debugger, profiler, etc.).  Codasip has made various enhancements in order to optimize Studio and the CodAL language for the generation of RISC-V cores. It has launched the 7th generation of its Studio adding significant new functionality and features, making it the most advanced and effective technology on the market for tailoring RISC-V processors to meet chip designers' application-specific needs.

11:10am - 11:35am 25 mins
Commercial/Open Source RISC-V Implementations
Ultra-Low-Power Open-Source Core to Boost the Spread of RISC-V in China 超低功耗开源处理器核助力RISC-V在中国的爆发
  • Bob Hu - Open Source HummingBird E203 Developer, Open Source HummingBird E203 RISC-V Processor Core Group
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The opensource Hummingbird E203 core developed by Bob Hu has been established over half a year.   The opensource E203 core is a ultra low-power core which is perfect for the entry-level student of beginner to study RISC-V, and perfect as the university class program. I will systematically introduce:   

  • The details of this core, including  its features, pipeline structures, and the opensource SoC.   
  • The relevant boards, and the plan for a series of FPGA based board to play with E203 core for beginners.    
  • The published 1st Chinese RISC-V Book, and the next publish-ongoing Chinese Book.
11:35am - 11:50am 15 mins
Commercial/Open Source RISC-V Implementations
HWPE: A CNN accelerator for RISC-V HWPE: 一个为RISC-V实现的CNN加速器
more
11:50am - 12:30pm 40 mins
Commercial/Open Source RISC-V Implementations
Panel Discussion 圆桌讨论
12:30pm - 1:15pm 45 mins
Networking Lunch 午餐
1:15pm - 1:40pm 25 mins
RISC-V Architecture
Using RISC-V in high computing, ultra-low power, programmable circuits for inference on battery operated edge devices 面向边缘计算的,基于RISC-V的高性能、超低功耗应用处理器及其架构
  • Eric Flamand - CTO, Greenwaves Technologies
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Today's ultra-low power edge devices that need to operate for a long period of time on a battery are limited to relatively data poor sensors such as temperature, pressure, motion. For the next generation enabling data rich sensors for these edge devices opens great opportunities but also poses some serious challenges. The focus of this presentation and paper will be a step by step analysis of how hardware resources are used (vectors, parallelization, synchronization, power management, memory management) to overcome these challenges.

1:40pm - 2:05pm 25 mins
RISC-V Architecture
OpenPrefetch: Let There Be Industry-Competitive Prefetching in RISC-V Processors OpenPrefetch – 构造一个工业级的RISC-V处理器预取方案
  • Bowen Huang - Assistant Engineer, Institute of Computing Technology, Chinese Academy of Sciences.
  • Yungang Bao - Professor, ICT
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Prefetching is a well-proven performance-boosting architecture technique. Major industry vendors have already adopted multiple prefetching designs in commercial processors; however, the RISC-V processors still lack prefetching, therefore it may put RISC-V at an uncompetitive position in terms of performance.      Recently, the community of RISC-V begins to pay attention to prefetching designs,  but we find that evaluations of previous prefetching designs in published literature are incompleted, inconsistent, and sometimes exaggerated.  In the light of it, we poured our resources to launch OpenPrefetch, aiming at enhancing the performance of RISC-V processors by industry-competitive prefetching,  and at the same time, providing a fair platform and baseline for prefetching-related research.

2:05pm - 2:20pm 15 mins
RISC-V Architecture
Ways to Reduce RISC-V Soft Processor Footprint 减少RISC-V软核处理器资源占用的若干方法
  • Ruigang Wan - Developer, Chengdu University
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With the growing of microelectronics technology, many FPGA design has some unused logic elements. In order to cost the entire system down and develop more easily. Use footprint optimized soft processor is common practice. Although vendor provided soft processor has been designed as small as it can. But, most of the vendor provided soft processor can’t be modify, it is not suitable for customization design. I decided to take advantage of the RISC-V architecture and build a series of RISC-V processor which focus on optimize footprint and timing for FPGA. This paper describes several ways to reduce RISC-V soft processor's footprint on FPGA, e.g. to utilize FPGA architecture itself, or cut down wide combinational logic into narrow and shift registers, or sharing memory with other logic and so on. Which allows developers to fit small RISC-V processor into these unused logic elements. Make the entire system budget and easy to develop.

2:20pm - 2:45pm 25 mins
RISC-V Security
Firmware Freedom: Coreboot for RISC-V 自由的固件: Coreboot的RISC-V移植
  • Xiang Wang - Open Source Security Consultant, TYA infotech
  • Shawn Chang - Open source security consultant, HardenedLinux
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Coreboot is a decades-old libre/free and open source firmware implementation and it supports multiple architectures. RISC-V is an open ISA standard and it's likely to solve the auditable firmware problem in the future. This presentation is introduce how Coreboot can run w/ RISC-V hardware and reports some updates about Hifve1 and Sifive Unleashed from the Coreboot community.

2:45pm - 3:10pm 25 mins
RISC-V Security
Defeating the Recent AnC Attack in RISCV SoC 在RISC-V SoC中防御新近出现的AnC攻击
  • Rui Hou - Professor, Institute of Information Engineering, Chinese Academy of Sciences
  • Xiaoxin Li - Student, Institute of Information Engineering, Chinese Academy of Sciences
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New defenses are proposed to defend against the recent AnC attack. RCL-hash scheme remaps the cache layout using a hash function on the cache indexes.This is an effective defense when the OS actively randomizes its physical to virtual page mapping. PTE-isolation scheme isolates the PTE from normal data in the cache hierarchy.Implemented in the BOOM SoC, the results show that the RCL-hash scheme incurs a small overhead in execution time and the overhead of the improved PTE-isolation scheme is also acceptable.

3:10pm - 3:50pm 40 mins
Networking Break 茶歇
3:50pm - 4:15pm 25 mins
RISC-V Ecosystem
Fedora on RISC-V - Status update Fedora在RISC-V上的最新进展
  • Wei Fu - Software Engineer, Red Hat
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This presentation will talk about status of Fedora on RISC-V, like bootstrap, Koji system, Key components status and show a demo of Fedora on Unleashed(and QEMU). Will also talk about "Why Fedora on RISC-V first, but not RHEL or CentOS". Finally, rise a proposal about  "Industry standard RISC-V server".

4:15pm - 4:40pm 25 mins
RISC-V Ecosystem
SylixOS (SMP RTOS) running on RISC-V 面向对称多处理器的RTOS SylixOS的RISC-V移植
  • JinXing Jiao - CTO, ACOINFO
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SylixOS is an open source, embedded real-time operating system from China.  

SylixOS Introduction: 

  1. Developed since 2006
  2. Open source, GPL license 
  3. Multiple processor architecture support, such as RISC-V, ARM, x86, MIPS, PowerPC, SPARC, C-SKY
  4. Support symmetric multi-processor(SMP), such as Freedom U540 
  5. POSIX specification 
  6. Excellent real-time performance (time complexity of task scheduling and switching algorithm is O(1))
  7. Support dynamic loading applications, dynamic link libraries, and kernel modules
  8. Support third-party GUI graphics libraries, such as Qt, MiniGUI 
  9. Support for many standard file systems: TPSFS (power loss), FAT, YAFFS, ROOTFS, PROCFS, NFS, ROMFS, etc 
  10. Support AF_UNIX, AF_PACKET, AF_INET, AF_INET6 protocol domain 
  11. It can be started in 1~2 seconds according to project requirements 

After our engineers' efforts, SylixOS was finally ported to Freedom U540.  This talk will share with you the status of SylixOS porting on RISC-V.


4:40pm - 5:05pm 25 mins
RISC-V Ecosystem
RT-Thread/RISC-V RT-Thread的RISC-V移植
  • Yongxiang Liang - Engineer, RT Thread
  • Bernard Xiong - CEO, RT Thread
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熊谱翔大学毕业后在上海贝尔和阿尔卡特任职,从大学到就业期间,熊谱翔就一直从事嵌入式设备及实时操作系统工作并积累相关经验。2006年,推出了RT-Thread,开启了国产RTOS创业历程。

5:05pm - 5:30pm 25 mins
RISC-V Ecosystem
Deep Learning showcased on RISC-V with Linux using the Mi-V Unleashed kit 在Mi-V Unleashed Kit上的基于Linux/RISC-V的深度学习演示
  • Krishnakumar R - Senior Staff Engineer, Product Marketing, Microsemi
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This presentation will highlight the RISC-V hardware to support Linux development. The Mi-V Unleashed expansion board and the SiFive Unleashed board together enable one to create a RISC-V Linux PC.  Based on this hardware, a deep learning IP will be explained. This consists of a deep learning IP using the PolarFire FPGA with the SiFive RISC-V U54 running Linux.  Benchmarks and other design statistics will be shown.

5:30pm - 5:45pm 15 mins
RISC-V Ecosystem
Perf-V creative board designed for the RISC-V community with future ecosystem support 为RISC-V社区设计的Perf-V创意开发板及其未来生态支持
  • Hualong Zhao - SVP, Perfxlab company
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Perf-V creative board is designed for the RISC-V community and developers by PerfXLab. It integrates Arduino compatible interface, PMOD interface and high-speed IO connector. It equips Artix-7 FPGA manufactured by Xilinx and 128/256MB DDR3 memory. The special User_JTAG is separated from FPGA JTAG connector for debugging and programming RISC-V soft cores. It also integrates dual 12-bit 1MSPS AD converter which is suitable for IoT data acquisition scenario. We also provide several expanding boards such as USB, HDMI, camera, Ethernet, etc. All these expanding boards dramatically enhance the Perf-V deployment capability for various application demands. Perf-V is suitable for prototyping, development, IoT and education. Further, considering for better support Perf-V ecosystem, we are planning to release our new RISC-V core, X-core. X-core is a five-stage pipeline processor core fully based on RISC-V 32 ISA with I-Cache and D-Cache. Basic X-core edition will be open source in the summer of 2018.

5:45pm - 6:00pm 15 mins
Closing Session 总结
8:00am - 8:40am

Registration & Networking

Showing of Streams
Showing of Streams
10:15am - 10:45am

Networking Break 茶歇

Showing of Streams
12:30pm - 1:15pm

Networking Lunch 午餐

Showing of Streams
Showing of Streams
3:10pm - 3:50pm

Networking Break 茶歇

Showing of Streams
5:45pm - 6:00pm

Closing Session 总结