Dates And Venue For 2019 Will Be Announced Soon
THANKS TO EVERYONE WHO ATTENDED RISC-V TOKYO 2018
THE RISC-V DAY TOKYO
The microprocessor IP market is being disrupted, and RISC-V is fast gaining support as an attractive license-free approach to architecture. This open standard collaboration will transform and reshape established world order of the silicon market, and the implications of this change will resonate from Silicon Valley to Silicon Fenn and beyond.
Now is the time to explore this disruptive technology, learn about its benefits, and understand the commercial implications for the strategy of your company and for those of your competitors.
The expansive and international RISC-V ecosystem met in Tokyo, October 2018 to discuss current and prospective RISC-V projects and implementations, as well as influence the future evolution of the instruction set architecture (ISA).
Thanks to our Organizers and Program Committee!
- Shumpei Kawasaki, SH Consulting
- Naomi Tsujioka, SH Consulting
- Alex Guo, Jinglue Semiconductor
- Charlie Su, Andes Technologies
- Xiaoning Qi, C-sky
- Yaoko Nakagawa, Hitachi
- Eiji Kasahara, Esperanto Tech
- Akira Tsukamoto, National Institute of Advanced Industrial Science and Technology
- Keishi Takebe, Japan Embedded Systems Technology Association
- Rick O'Connor, RISC-V Foundation
Download the agenda in Japanese
2018 EVENT HIGHLIGHTS INCLUDED:
In-depth Technical Education
One full day of presentations and updates on the RISC-V architecture, commercial and open-source implementations, software and silicon, vectors and security, applications and accelerators, simulation infrastructure and much more.
Leaders in the Ecosystem
The speaking lineup included leaders from the major players in the RISC-V ecosystem, including the leading technology companies and research institutions driving the RISC-V ISA specification.
Networking
Attendees enjoyed our networking lunches & breaks and were able to take time to relax and mingle with their peers.