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18 October 2018
Keio University,
Yokohama

JOIN US ON OCTOBER 18 AND LEARN HOW THE FREE AND OPEN RISC-V ARCHITECTURE IS REVOLUTIONIZING THE SILICON MARKET AND BEYOND!

Don't Miss Out!

All Paid Attendees Receive a Copy of the Japanese Edition of the RISC-V Reader  by David Patterson & Andrew Waterman. ($20 Value!)

THE RISC-V DAY TOKYO


The microprocessor IP market is being disrupted, and RISC-V is fast gaining support as an attractive license-free approach to architecture. This open standard collaboration will transform and reshape established world order of the silicon market, and the implications of this change will resonate from Silicon Valley to Silicon Fenn and beyond.

Now is the time to explore this disruptive technology, learn about its benefits, and understand the commercial implications for the strategy of your company and for those of your competitors.

Join the expansive and international RISC-V ecosystem in Tokyo this October to discuss current and prospective RISC-V projects and implementations, as well as influence the future evolution of the instruction set architecture (ISA).

Thanks to our Organizers and Program Committee!

  • Shumpei Kawasaki, SH Consulting
  • Naomi Tsujioka, SH Consulting
  • Alex Guo, Jinglue Semiconductor
  • Charlie Su, Andes Technologies
  • Xiaoning Qi, C-sky
  • Yaoko  Nakagawa, Hitachi
  • Eiji Kasahara, Esperanto Tech
  • Akira Tsukamoto, National Institute of Advanced Industrial Science and Technology
  • Keishi Takebe, Japan Embedded Systems Technology Association
  • Rick O'Connor, RISC-V Foundation


Download the agenda in Japanese

WHAT TO EXPECT AT THE RISC-V DAY TOKYO

In-depth Technical Education

One full day of presentations and updates on the RISC-V architecture, commercial and open-source implementations, software and silicon, vectors and security, applications and accelerators, simulation infrastructure and much more.


Leaders in the Ecosystem

The speaking lineup will include leaders from the major players in the RISC-V ecosystem, including the leading technology companies and research institutions driving the RISC-V ISA specification.


Networking

No RISC-V Day is complete without our networking lunches & breaks where you can take time to relax and mingle with your peers and industry leaders.

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