The RISC-V software ecosystem has made great strides over the past year: binutils, GCC, glibc, and Linux are all upstream, and distributions including Fedora and Debian are well on their way towards initial support for the RISC-V ISA. This talk will discuss the current state of the RISC-V software ecosystem, what the big problems are right now, and how you can get involved.

In this talk we will cover the latest updates to the Vector ISA specification

We will describe some of the challenges in formalizing a specification of the RISC-V ISA, the current status, the uses to which we are putting the formalization, and the next steps (including integration with the formal Memory Model).

Hardware Software Co-design is joint design of hardware and software architectures, which encompasses performance analysis, scheduling and allocation of resources. But all too often hardware decisions are made at the convenience of hardware schedules and resources, leaving the software enablement in a sub optimal position of inefficient architectures and late deliveries. “Shift left” software development using FPGA accelerated emulation can identify performance issues and bottlenecks earlier. But its still an afterthought to design decisions made earlier. Software engineers using hardware construction tools and software use cases can provide more direct recommendations to the SoC design earlier in the process. This talk will discuss how these techniques have been incorporated into an industrial design flow with some specific RISC-V lessons learned and opportunities for additional improvement.

In November 2017, Martin Fink, CTO of Western Digital, keynoted at the RISC-V Summit in Milpitas, California. During his presentation, he noted that as Big Data applications emerge to enable technologies of the future: autonomous driving, artificial intelligence (AI), machine learning, the need for more special-purpose compute capabilities are required.
Data-intensive workloads create opportunities and a new breed of purpose-built processing requirements to pave the path to bring data closer to compute power. The ability to compute data, and obtain real-time intelligence at the edge of the network where the data lives is important to support new, creative applications.

In this updated presentation, Fink will outline why RISC-V has the capabilities, foundation, ecosystem, and openness required for storage-centric architectures that support these applications. This presentation will discuss these trends and how Western Digital is embarking on its journey to use RISC-V to pave the pathways of data in emerging technologies. Specifically, Fink will highlight the progress Western Digital has made since November, delve into licensing, and highlight the open interface aspects that RISC-V presents.

re debugging (synchronous SMP and asynchronous AMP), in heterogeneous chips with other architectures. (3) Support for JTAG DTM, other DTM variants and implementations without dedicated DTM.

WIth 64-bit RISC-V support recently added to the Renode open source simulation framework, users can now build mixed 32- and 64-bit ARM and RISC-V (and other) simulations in one virtual time domain, and develop production-ready software in a continuous integration environment to bridge the gap for RISC-V adoption. The presentation will talk the audience through one example virtual system including multiple SiFive Freedom U54 RV64GC Linux and Microsemi Mi-V / SiFive HiFive1 Zephyr nodes, and highlight how Renode's rapid prototyping, improved debugging, code-sharing, co-development features can be used for practical use cases today.  The possibility to build simulated platforms using scripts, to add plugins, peripheral devices and I/O in runtime and to extend functionalities through plugins is a good match for complex Linux-capable SoCs and the associated tooling.  Thanks to its extensibility, Renode is already used by several members of the Foundation for PoCs, performance analyses and prototyping, and the availability of a 64-bit platform will enable a wider adoption among RISC-V developers.

The first version of GDB for RISC-V was accepted upstream at the end of February. This provides basic bare metal debugging support and has a more than 99% regression test pass rate with the GDB simulator (currently out-of-tree).  The first part of this talk will provide an update on the state of RISC-V GDB upstream. - improving the test results for remote debugging using a GDB server. - Adding target description support for the RISC-V variants - Adding non-DWARF stack unwinding - Upstreaming a GDB simulator. - Adding Linux support  The second half of the talk will look at improving GDB's support for bare metal multicore systems. This is particularly important to RISC-V, with widespread use of "minion" clusters to drive peripherals. - Attaching to multicore systems where the cores are already running - Improving support for complex memory structures, where some regions are shared with all (or some) cores and others are private. - Extending the user interface, so GDB can talk about cores without mentioning threads or processes.  We are working on a free and open source demonstrator for this technology using the latest PULP implementation. We will give an update on progress with this work.

Complex SoC's contain not just multi-core processors but multiple clusters of processors from multiple vendors utilizing different architectures. RISC-V has gained attention across a wide range of end markets and applications, and some of the emerging markets requirements are themselves at the forefront of innovation and exploration. Early software development is key to efficiently capitalize on these new opportunities while presenting RISC-V developers with additional challenges both in SoC development such as customizable functions and with the end application development.  To accelerate the time to market, virtual platforms and fast simulators can assist with early software development. In such platforms, complete visibility of the whole system is available greatly aiding the development of functional software. Migrating to the physical hardware, when it is available, with as near similar visibility using the same development environment will greatly increase product integration.  The same environment can be used for all the stages of the system development process: RTL simulation, virtual platform simulation, and SoC/FPGA hardware.

In this talk, I present the world's first multi-core RISC-V Linux development board, HiFive Unleashed.  The board features SiFive's FU540-C000 silicon built in TSMC 28nm alongside 8GB DDR4 memory, gigabit ethernet port, 32MB quad-SPI flash, microSD card for removable storage, microUSB for debug and serial communication, and an FMC connector for expansion add-in cards.  I will also talk about the RISC-V software efforts that went into the board, and show cool demos.

Explain the hardware features available on the PolarFire FPGA expansion board for HiFive Unleashed. Learn details about the purpose built Microsemi expansion board for Linux software development.  Numerous common peripheral options will be revealed and proprietary expansion options too. See how you can develop custom accelerators for the HiFive Unleashed FU-540.  One can develop Linux drivers for PCIe cards.  For users who want to go further, the scripted FPGA development flow will be shown.  This allows custom peripherals to be implemented.

This talk is a follow-up on a talk in the 4th RISC-V Workshop at CSAIL/MIT with a similar title, with an update on the current status after major recent developments in the RISC-V software landscape.  We will present the ongoing work to make Debian available for RISC-V based devices, creating what is known as a "port" with Linux as kernel. The current target is the 64-bits little-endian ABI with the "General" set of standard extensions (RV64G), although others could be considered if hardware becomes available.  The aim is to integrate it fully into the Debian infrastructure, in order to offer software readily available to end-users and receive continuous updates.  Debian is one of the oldest and largest curated collections of free and open source software (FOSS), a “GNU/Linux distribution” (with Hurd and the FreeBSD kernel partially supported).  It currently contains over 20,000 source packages which are built and mirrored across the world and ready to use as pre-compiled software by users, research centres, hosting providers, companies and other institutions.  Many other well-known “distributions” or “platforms” are built on top of Debian, such as Raspbian, Ubuntu, Steam OS, Tails, Knoppix and Maemo.  Major Stable releases happen every two years.  They provide installers and more than 95% of the pre-compiled software for all the “officially supported” ports, with security support for these versions for many years after the release.  â€œUnsupported” or “unofficial” ports are those which are not part of Stable releases because they are new, incomplete or too old, but are still part of the infrastructure for as long as there are people working on them.  Pre-compiled packages from these ports are also publicly available, with new packages and updated versions being built continuously as they arrive in the common archive for all ports.  Currently, 10 ports (architecture ABIs) are officially supported in the last Stable release ─ x86, ARM, MIPS, PowerPC and s390x, with several combinations of 32 and 64 bits and endian-ness flavours.  Ports not officially supported now but part of the infrastructure are among others Alpha, HPPA, Motorola 68k, SuperH 4 and SPARC 64, and ports based on the FreeBSD kernel and Hurd (instead of Linux) for x86.

Fedora is a popular Linux distribution which focuses on leading innovation, freedom, integrating new technologies early, and working with upstream communities.  RISC-V is a natural fit.  In this talk we will cover the status of Fedora on RISC-V, future directions, and our thoughts on RISC-V as a Unix server platform.

With the advancements in CMOS scaling it is now feasible to fit >10^7 transistors per mm^2. Furthermore active power per operation has dropped by >103 compared to early CMOS nodes. This has presented the opportunity to fit a computer system in a sub-mm^2 foot-print, at very low cost. Because if its size and cost advantages, it will open new modes of deployment, especially as related to IoT devices. We present a RISC-V based device in 14nm technology node whose design is optimized to meet the requirements of IoT deployment as a secure data source. Our sub-mm size device incorporates a 32-bit RISC-V processor, memory, photo-voltaic power source and optical communication. We describe the modifications made to the open source SoC designs to meet the requirements of a secure IoT device, such as the addition of hardware accelerator for authentication function, a custom memory interface for XIP, and flexible serial communication interface design to allow for wider clock frequency variation from on-chip clock generation. Our 1st processor silicon successfully booted on a sub-mm^2 package.

4:30 PM - 5:00 PM

• HW-Assisted Task Scheduling on Linux-Enabled Multicore Rocket Chip, Guido Araujo and Lucas Morais      
• On the Path to a Secure Boot Solution for RISC-V, Derek Atkins 
• Implementing RISC-V Binary Utilities Using CGEN, Mary Bennett
• Diving into the RISC-V LLVM Backend, Alex Bradbury
• asureISG Instruction Stream Generator for RISC-V Processors, Arun Chandra and Mike Bartley
• Two-level Energy-Efficient and Timing-Relaxed L1.5 I$ Design in Ultra-Low-Power RISC-V Cluster, Jie Chen    
• Verifying PULPino RISCY Core for a Google Accelerator with STING, Shubhodeep Roy Choudhury, Valtrix Technologies Pvt. Ltd
• How You Get your RISC-V Design Off the Ground, Martin Croell  
• TCCF: Tightly-Coupled Co-simulation Framework for RISC-V Based Systems, Alberto Dassatti   
• The First Open Platform for Energy-Efficient SoCs based on RISC-V, Nicolas Gaude and Hai Yu 

5:00 PM - 5:30 PM     

• Enhancements to Tools for Automated Generation of RISC-V Processors, Chris Jones and Zdenek Prikryl     
• ApproxRISC -- An Approximate Computing Infrastructure for RISC-V, Tiago Trevisan Jost and Anca Molnos
• Automated Verification of RISC-V-conform Floating-Point Modules, Felix Kaiser    
• Developing a Libre and Commercial Mass-Volume RISC-V SoC, Luke Leighton 
• Enabling Rust Flow and Framework for RISC-V Architectures, Heng Lin
• RISC-V Hardware Extensions for Secure Hardware/Software Co-design Maja Malenko and Marcel Baunach    
• Exploring Soft-Processor Accelerator Integration with the RISC-V ISA and the Taiga Processor, Eric Matthews and Lesley Shannon
• RISC-V S10: Revisiting the Smallest Program, Paulo Matos
• Pulpino Featuring Klessydra Cores: Yet Another RISC-V Microcontroller Core Family for IoT, Supporting Bare-Metal Multi-Threaded Execution, Mauro Olivieri        
• Introducing Chisel to IC Design Curriculum at the Faculty of Electrical Engineering in Banja Luka, Aleksandar Pajkanovic
• Hot Plug CPU in RISC-V, Atish Kumar Patra

5:30 PM - 6:00 PM

• Securing a RISC-V core for IoT Applications with Dynamic Information Flow Tracking, Davide Rossi
• STING -- A Complete RISC-V Functional Verification Solution, Shubhodeep Roy and Shajid Thiruvathodi  
• Dynamic Language Runtimes on RISC-V, Boris Shingarov 
• Practical Aspects of Using Open-Source SCR1 Core, Andrey Smolyarov, Syntacore and Ekaterina Berezina,  Syntacore
• Defeating the Recent AnC Attack by Simply Hashing the Cache Indexes -- Implemented in a BOOM SoC, Wei Song and Rui Hou
• A Processor Trace Interface for RISC-V to Support Policy Enforcement (In Addition to Supporting Debugging and other Dynamic Analysis), Greg Sullivan and Steve Milburn
• Test Program Generator MicroTESK for RISC-V, Andrei Tatarnikov and Alexander Kamkin
• The M3 architecture under RISC-V, Robert Trout    
• Quad-core Linux-Capable SCR5-based SDK, Vasily Varaksin and Ekaterina Berezina
• Security Trend: CoT, RoT and RISC-V, Danny Ybarra      
• Enabling RISC-V Support on MaxineVM, Foivos S. Zakkak and Christos Kotselidis