RISC-V Workshop Barcelona is part of the Informa Tech Division of Informa PLC

This site is operated by a business or businesses owned by Informa PLC and all copyright resides with them. Informa PLC's registered office is 5 Howick Place, London SW1P 1WG. Registered in England and Wales. Number 3099067.

Informa
keyboard_arrow_right

Day One

keyboard_arrow_leftSearch & Filter
search

Day One

search
8:00am - 8:45am45 mins
Download the Proceedings for the RISC-V Workshop Barcelona
    8:45am - 9:00am15 mins
    Welcome Address & Foundation Overview
    • Rick O' Connor - Executive Director, RISC-V Foundation
    9:00am - 9:25am25 mins
    State of the Union: RISC-V
    • Krste Asanovic - Professor / Chief Architect, UC Berkeley | SiFive
    9:25am - 9:55am30 mins
    The State of RISC-V Software
    • Palmer Dabbelt - Vice Chair RISC-V Software Working Group| RISC-V Software Team Lead, SiFive
    • Arun Thomas - Chair, RISC-V Software Working Group | Principal Scientist, Draper Laboratory
    9:55am - 10:25am30 mins
    Vector ISA Proposal Update
    • Roger Espasa - Chair, Program Committee | Chief Architect, Esperanto Technologies
    10:25am - 10:40am15 mins
    The RISC-V Formal Specification Technical Group: Progress Report
    • Rishiyur Nikhil - Chief Technology Officer, Bluespec
    10:40am - 10:55am15 mins
    RISC-V Memory Consistency Model Task Group Update
    • Daniel Lustig - Senior Research Scientist, NVIDIA
    10:55am - 11:20am25 mins
    Networking Break
      Keynotes
      11:20am - 11:45am25 mins
      Software Drives Hardware, lessons learned and future directions
      • Robert Oshana - VP Software Engineering, R&D, NXP
      11:50am - 12:15pm25 mins
      Unleashing the Power of Data with RISC-V
      • Martin Fink - Chief Technology Officer, Western Digital
      12:15pm - 1:30pm75 mins
      Networking Lunch
        1:30pm - 1:45pm15 mins
        RISC-V Debugging: Custom ISA Extensions, Multicore, DTM Variants
        • Markus Goehrle - System Engineer, Lauterbach Engineering GmbH
        1:45pm - 2:00pm15 mins
        GDB for RISC-V: Extending Support for Bare Metal Multi-core Debugging
        • Jeremy Bennett - CEO, Embecosm
        2:00pm - 2:15pm15 mins
        A Common Software Development Environment for Many-core RISC-V based Hardware and Virtual Platforms
        • Gajinder Panesar - CTO, UltraSoC
        • Simon Davidmann - CEO, Imperas
        2:15pm - 2:30pm15 mins
        HiFive Unleashed: World's First Multi-Core RISC-V Linux Dev Board
        • Yunsup Lee - Vice Chair, Program Committee | CTO, SiFive
        2:30pm - 2:45pm15 mins
        HiFive Unleashed Expansion Options and Capabilities
        • Ted Marena - Director of Marketing, Microsemi
        2:45pm - 3:00pm15 mins
        Simulating Heterogeneous Multi-node 32-bit and 64-bit RISC-V Systems Running Linux and Zephyr with the Open Source Renode Framework
        • Michael Gielda - VP Business Development, Antmicro
        3:00pm - 3:25pm25 mins
        Networking Break
          3:25pm - 3:55pm30 mins
          Debian GNU/Linux Port for RISC-V 64-bit
          • Manuel Fernandez Montecelo - Member, Debian Community
          3:55pm - 4:10pm15 mins
          Fedora on RISC-V
          • Richard Jones - Emerging Technology, Red Hat
          • David Abdurachmanov - Software Engineer, Independent
          4:10pm - 4:25pm15 mins
          Smallest RISC-V Device for Next-Generation Edge Computing
          • Seiji Munetoh - Senior Researcher, IBM
          4:25pm - 4:30pm5 mins
          Video: The MareNostrum
            4:30pm - 6:00pm90 mins
            Poster / Demo Previews
              6:00pm - 9:00pm180 mins
              Networking Reception, Posters Sessions and Demos
                Tutorial Day
                NextDay Two
                Filter
                Streams
                Formats
                Choose Day