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18th - 19th July 2018
Indian Institute of Technology Madras,
Chennai

Join the RISC-V Revolution!

Attend the RISC-V Workshop Chennai and be part of the disruptive force transforming the microprocessor IP market through open standard collaboration

THE RISC-V WORKSHOP CHENNAI


The microprocessor IP market is being disrupted, and RISC-V is fast gaining support as an attractive license-free approach to architecture. This open standard collaboration will transform and reshape established world order of the silicon market, and the implications of this change will resonate from Silicon Valley to Silicon Fenn and beyond.

Now is the time to explore this disruptive technology, learn about its benefits, and understand the commercial implications for the strategy of your company and for those of your competitors.

Join the expansive and international RISC-V ecosystem in Chennai this July to discuss current and prospective RISC-V projects and implementations, as well as influence the future evolution of the instruction set architecture (ISA).

WHAT TO EXPECT

In-depth Technical Education

Two full days of presentations and updates (18th and 19th July) on the RISC-V architecture, commercial and open-source implementations, software and silicon, vectors and security, applications and accelerators, simulation infrastructure and much more.

Leaders in the Ecosystem

The speaking lineup will include leaders from the major players in the RISC-V ecosystem, including the leading technology companies and research institutions driving the RISC-V ISA specification.

Networking Reception

No RISC-V workshop is complete without our networking reception where you can take time to relax and mingle with your peers.

Demo Zone

During the networking reception you can also visit demo zone where there will be live product and service demos allowing you to explore the latest innovations on the market.

Want to sponsor or exhibit at the RISC-V Workshop Chennai?

For more information download our sales prospectus or speak to a member of our team.