June 11 - 13, 2019
ETH Zurich,
Zurich
JOIN US IN JUNE 2019 AND LEARN HOW THE FREE AND OPEN RISC-V ARCHITECTURE IS REVOLUTIONIZING THE SILICON MARKET AND BEYOND!
RISC-V Workshop Zurich
The microprocessor IP market is being disrupted, and RISC-V is fast gaining support as an attractive license-free approach to architecture. This open standard collaboration will transform and reshape established world order of the silicon market, and the implications of this change will resonate from Silicon Valley to Silicon Fenn and beyond. Now is the time to explore this disruptive technology, learn about its benefits, and understand the commercial implications for the strategy of your company and for those of your competitors. Join the expansive and international RISC-V ecosystem in Zurich, June 2019 to discuss current and prospective RISC-V projects and implementations, as well as influence the future evolution of the instruction set architecture (ISA).
EVENT HIGHLIGHTS
In-depth Technical Education
Two full days of presentations and updates on the RISC-V architecture, commercial and open-source implementations, software and silicon, vectors and security, applications and accelerators, simulation infrastructure and much more.
Leaders in the Ecosystem
The speaking lineup will include leaders from the major players in the RISC-V ecosystem, including the leading technology companies and research institutions driving the RISC-V ISA specification.
Networking Reception
No RISC-V Workshop is complete without our networking lunches & breaks where you can take time to relax and mingle with your peers.
RISC-V STATE OF THE UNION
Watch Krste Asanovic, Professor/Chief Architect, UC Berkeley, RISC-V Foundation & SiFive Inc talk about RISC-V, State of the Union.
