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December 3 - 6, 2018
Santa Clara Convention Center,
Santa Clara, CA

JOIN US AND LEARN HOW THE FREE AND OPEN RISC-V ARCHITECTURE IS REVOLUTIONIZING THE SILICON MARKET AND BEYOND!

Meet the RISC-V Community and Experience Four Days of Presentations on RISC-V ISA Architecture, Commercial and Open-Source Implementations, Software and Silicon, Vectors and Security, Applications and Accelerators, Simulation Infrastructure and Much More.

SAVE $300!

BOOK BY Nov 23 AND SAVE UP TO $300 

Exhibition-Only Pass

A limited number of Free Exhibition-Only Passes are available to Engineering, Design, Developer, Senior Management professionals in the Silicon / Semiconductor industry and related verticals.

Members of the RISC-V Foundation are not eligible.Note this pass does not include access to keynotes, conference sessions or tutorials or food and beverage. For complete access to the conference, register for a conference pass.

RISC-V Linux Hackathon

Don't miss out on the RISC-V Linux Hackathon, happening Dec. 4-5 on the Expo Floor at the RISC-V Summit.

Watch as a team of 10 expert hackers create cutting edge applications on a soft RISC-V CPU running Linux on the low-cost Avalanche FPGA board. Thanks to Western Digital for organizing!

Parties & Special Events


Our networking events and parties will offer you the opportunity to network with your peers and industry leaders. Don’t miss such events as: 

  • RISC-V Summit Welcome Party | 5pm – 7pm, Dec 3 | Sponsored by Ashling
  • Expo Hall Opening Night Happy Hour | 5:30pm – 7pm, Dec 4
  • The Innovation Celebration | 7pm – 10pm | Sponsored by SiFive & Western Digital

Guided by Leaders in the Ecosystem


The conference program for the RISC-V Summit was developed and selected by leaders in the RISC-V ecosystem. 

Program Co-Chairs:

  • Zvonimir Bandic, Sr. Director, Next Generation Platform Technologies, Western Digital and member of the Board of Directors, RISC-V Foundation

  • Rob Oshana, VP, Software Engineering Research and Development, Microcontroller Group, NXP Semiconductors

Advisory Board members:

  • Stephen Bates , PhD, Chief Technology Officer, Eideticom

  • Yunsup Lee, Chief Technology Officer, SiFive

  • Borivoje Nikolic, Professor, Department of Electrical Engineering and Computer Sciences, University of California at Berkeley

  • Rick O'Connor, Executive Director, RISC-V Foundation

DOWNLOAD AGENDA

FEATURES AND HIGHLIGHTS FOR 2018

In-depth Technical Education

Three full days of presentations and updates on the RISC-V architecture, commercial and open-source implementations, software and silicon, vectors and security, applications and accelerators, simulation infrastructure and much more.

3 Dec 2018: Pre-Conference Training
4 - 5 Dec 2018: Conference and Exhibition
6 Dec 2018: RISC-V Foundation Member Meetings


Leaders in the Ecosystem

The speaker lineup includes leaders from the major players in the RISC-V ecosystem, including the leading technology companies and research institutions driving the RISC-V ISA specification.

Parties and Networking

Our networking events and parties will offer you the opportunity to network with your peers and industry leaders. Don’t miss such events as: 

  • RISC-V Summit Welcome Party | 5pm – 7pm, Dec 3 | Sponsored by Ashling
  • Expo Hall Opening Night Happy Hour | 5:30pm – 7pm, Dec 4
  • The Innovation Celebration | 7pm – 10pm | Sponsored by SiFive & Western Digital
RISC-V Linux Hackathon

Stop by the Expo Hall on Dec 4-5 and check out the RISC-V Linux Hackathon, sponsored by Western Digital, where the 10-member hackathon team will be hacking on a soft RISC-V CPU running Linux on the low-cost Avalanche FPGA board.

Jam Packed Expo Hall

The first-ever RISC-V Summit will also feature a jam-packed expo hall where leaders in the ecosystem will share live product demos and future plans for RISC-V technology, allowing you to explore the latest innovations on the market.

Member Meetings

Reserved for members of the RISC-V Foundation on December 6, 2018. Final member meeting agenda to be published prior to the event.

NUMBERS AT A GLANCE

1000+ ATTENDEES
FROM THE EMERGING RISC-V ECOSYSTEM
65+ SPEAKERS
SHARING DEVELOPMENTS ON THE RISC-V ISA
35+ EXHIBITORS
SHOWCASING THE LATEST PRODUCTS AND SOLUTIIONS

RISC-V Summit Sponsorship and Exhibition Opportunities

Meet 1000+ Potential Customers And Position Yourself As An Industry Leader In The RISC-V Ecosystem At The RISC-V Summit 2018 Exhibition

RISC-V Summit expo hall will share live product demos and future plans for RISC-V technology, allowing attendees to explore the latest innovations on the market. We have a number of packages available to suit any budget or requirement. To book a booth or to find out more about sponsorship opportunities get in touch.

VIEW HIGHLIGHTS FROM RISC-V GLOBAL EVENT SERIES 2018


View highlights from our RISC-V Global Event Series

Headline Sponsor

Emerald

Gold Sponsor

Happy Hour Sponsor

Plan Your Visit - The perfect location to meet with your peers and exchange learning