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The RISC-V Revolution


RISC-V Summit is brought to you by RISC-V International and Informa Tech.

Founded in 2015, RISC-V International is now comprised of over 300 members and over 200 corporate/institutional members building the first open, collaborative community of software and hardware innovators powering innovation at the edge forward. Born in academia and research, RISC-V ISA delivers a new level of free, extensible software and hardware freedom on architecture, paving the way for the next 50 years of computing design and innovation.

RISC-V International, a non-profit corporation controlled by its members, directs the future development and drives the adoption of the RISC-V ISA. Members have access to and participate in the development of the RISC-V ISA specifications and related HW / SW ecosystem. RISC-V International has a Board of Directors comprising seven representatives from Bluespec, Inc.; Google; Microsemi; NVIDIA; NXP; University of California, Berkeley; and Western Digital.

RISC-V: The Free and Open RISC Instruction Set Architecture


NEW TO RISC-V?
NEW TO RISC-V?

RISC-V is an open, free ISA enabling a new era of processor innovation through open standard collaboration. Born in academia and research, RISC-V ISA delivers a new level of free, extensible software and hardware freedom on architecture, paving the way for the next 50 years of computing design and innovation.

The royalty-free ISA supports new and more specialized microprocessor designs that soon will appear in traditional computing devices as well as wearables, home appliances, robotics, autonomous vehicles and factory equipment.


Want to learn more about RISC-V strategies, technologies & implementations? Newcomers to RISC-V, as well as the seasoned developers who are interested in broadening their toolsets, are invited to join us virtually for RISC-V Summit, December 8-10. Click the button below to register!

Register for RISC-V Summit
BENEFITS OF RISC-V
BENEFITS OF RISC-V

1) Unlocks architecture and enables innovation since RISC-V is a layered and extensible ISA, companies can easily implement the minimal instruction set, well defined extensions and custom extensions to create custom processors for these new and innovative workloads

2) Reduces risk and investment via leverage of established and common IP building blocks with a growing set of shared tools and development resources with an engaged development community.

3) Creates opportunities to create thousands of possible custom processors as implementation is not defined at the ISA level, but rather by the composition of the SoC and other design attributes. It’s possible to go big, small, powerful, or lightweight.

4) Accelerates time to market through collaboration and open source IP reuse, this not only reduces development expense, but accelerates time to market.

Already a RISC-V International Member?

Register for your discounted pass to attend RISC-V Summit!

The event kicks off December 8-10 - don't miss your chance to be part of the premier gathering of the RISC-V ecosystem.