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Key Sessions
Zvonimir Bandic
RISC-V and Chips Alliance Address new Compute Requirements
Western Digital | CHIPS Alliance
Rick O' Connor
Open Source Processor IP for High Volume Production SoCs: CORE-V Family of RISC-V Cores
OpenHW Group
Zdenek Prikryl
Processor IP Showcase with Andes Technology, CHIPS Alliance, Codasip, Shakti Project, SiFive, Syntacore, OpenHW Group
Codasip
Alex Bradbury
Production-ready RISC-V Support in LLVM/Clang 9.0 - How we Got There and What's Next
lowRISC CIC
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Wednesday, December 11

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Wednesday, December 11

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8:00am - 5:30pm570 mins
Registration
Registration
    8:30am - 8:35am5 mins
    Keynotes
    Welcome
      8:35am - 8:55am20 mins
      Keynotes
      RISC-V and Chips Alliance Address new Compute Requirements
      • Zvonimir Bandic - Sr. Director, Next Gen Platform Technologies | Chairman of the Board, CHIPS Alliance, Western Digital | CHIPS Alliance
      8:55am - 9:15am20 mins
      Keynotes
      Keynote
        9:15am - 9:35am20 mins
        Keynotes
        Keynote
          9:35am - 9:55am20 mins
          Keynotes
          Keynote
            9:55am - 10:15am20 mins
            Keynotes
            Open Source Processor IP for High Volume Production SoCs: CORE-V Family of RISC-V Cores
            • Rick O' Connor - Founder, President & CEO, OpenHW Group
            10:15am - 10:25am10 mins
            Keynotes
            Lightning Talks
              10:25am - 11:10am45 mins
              Keynotes
              Keynote Panel: Opportunity and Risks in Open Source Hardware
              • Tim Whitfield - VP Strategy Embedded and Automotive, ARM
              • Mendy Furmanek - IBM Director – OpenPOWER Processor Enablement; OpenPOWER President, IBM
              • Brandon Lewis - Editor-in-Chief, Open Systems Media
              • Krste Asanovic - Professor | Chief Architect, UC Berkeley | SiFive
              11:10am - 11:30am20 mins
              Keynotes
              Keynote
                11:30am - 12:50pm80 mins
                Networking
                Lunch Break
                  11:30am - 4:00pm270 mins
                  Expo
                  Expo Hall
                    12:50pm - 1:10pm20 mins
                    Hardware/Architecture
                    Enabling AI on Low Power Endpoint Devices Utilizing the QuickLogic and SiFive Freedom Aware Templates
                    • Brian Faith - CEO, QuickLogic Corporation
                    12:50pm - 1:10pm20 mins
                    Software
                    RISC-V Software State of the Union
                    • Palmer Dabbelt - Engineer, SiFive
                    12:50pm - 1:10pm20 mins
                    Security/Verification
                    Formal Methods for Hardware-software Integration on RISC-V Embedded Systems
                    • Samuel Gruetter - PhD student in Computer Science, MIT
                    1:20pm - 1:40pm20 mins
                    Hardware/Architecture.
                    Session Title to Come
                      1:20pm - 1:40pm20 mins
                      Hardware/Architecture
                      RISC-V For Heterogeneous Computing
                      • Zhipeng Huang - Principle Engineer, Huawei
                      1:20pm - 1:40pm20 mins
                      Software
                      Production-ready RISC-V Support in LLVM/Clang 9.0 - How we Got There and What's Next
                      • Alex Bradbury - Director, lowRISC CIC
                      1:50pm - 2:10pm20 mins
                      Hardware/Architecture.
                      Session Title to Come
                        1:50pm - 2:10pm20 mins
                        Hardware/Architecture
                        SweRV Cores Roadmap
                        • Zvonimir Bandic - Sr. Director, Next Gen Platform Technologies | Chairman of the Board, CHIPS Alliance, Western Digital | CHIPS Alliance
                        1:50pm - 2:10pm20 mins
                        Security/Verification
                        Modeling a State Machine Security Monitor for RISC-V Architecture
                        • Patrick Jungwirth - Computer Engineer, US Army Research Lab
                        • James Ross - Computer Engineer, US Army Research Lab
                        2:20pm - 2:30pm10 mins
                        Security/Verification
                        RISC-V Enclaves: A Clean Slate Approach To Linux Security
                        • Cesare Garlati - Co-Founder, Hex Five Security
                        2:20pm - 2:40pm20 mins
                        Software
                        Integrate RISC-V to build Open Common Automotive Platform
                        • Tiejun Chen - Technical Leader and Staff Engineer, VMware
                        2:20pm - 3:10pm50 mins
                        Hardware/Architecture
                        Processor IP Showcase with Andes Technology, CHIPS Alliance, Codasip, Shakti Project, SiFive, Syntacore, OpenHW Group
                        • Zdenek Prikryl - CTO, Codasip
                        • Kevin Chen - Senior Architect, Andes Technology
                        • Zvonimir Bandic - Sr. Director, Next Gen Platform Technologies | Chairman of the Board, CHIPS Alliance, Western Digital | CHIPS Alliance
                        • Arjun Menon - Senior Project Manager, ITT Madras | Shakti Project
                        • Yunsup Lee - CTO, SiFive
                        • Rick O' Connor - Founder, President & CEO, OpenHW Group
                        2:30pm - 2:40pm10 mins
                        Security/Verification
                        RISC-V: A New Zero-Trust Model for Cyber Resilient Avionics
                        • Kevin Kinsella - System Architect, Northrop Grumman
                        2:50pm - 3:00pm10 mins
                        Security/Verification
                        Can I Use Different Trace and Debug Sources to Create a Patchwork I can Actually Analyze?
                        • Thomas Andersson - Lead Emulation Architect, IAR Systems
                        • Robert Chyla - Lead Emulation Architect, IAR Systems
                        2:50pm - 3:10pm20 mins
                        Software
                        Coming Soon
                          3:00pm - 3:10pm10 mins
                          Security/Verification
                          Debugging on Homogeneous and Heterogeneous Multicore SoCs Containing a Mix of RISC-V and non-RISC-V Cores
                          • Hugh O'Keeffe - Engineering Director, Ashling
                          • Roisin O'Keeffe - VP, Business Enterprise, Ashling
                          3:10pm - 3:40pm30 mins
                          Networking
                          Networking Break
                            3:40pm - 4:00pm20 mins
                            Software
                            Headline Sponsor Western Digital presents: RISC-V Hypervisor Support
                            • Alistair Francis - Principal System Engineer, Western Digital
                            • Anup Patel - Technologist, Western Digital
                            3:40pm - 4:00pm20 mins
                            Security/Verification
                            RISC-V Processor Verification based on Open-source Framework and State-of-the-art Cloud-based Methodologies
                            • Lee Moore - Lead Engineer, Imperas
                            • Richard Ho - Principal Hardware Engineer, Google
                            3:40pm - 4:00pm20 mins
                            Hardware/Architecture.
                            Session Title to Come
                              3:40pm - 4:00pm20 mins
                              Hardware/Architecture
                              Innovation in CPU Architecture, Pushing Data from Edge to Cloud
                              • Caffrey Chen - Chief Processor Architect, Alibaba
                              4:10pm - 4:30pm20 mins
                              Software
                              Working Towards a Common C Library for Small RISC-V Systems
                              • Keith Packard - Partner, Altus Metrum, LLC
                              4:10pm - 4:30pm20 mins
                              Hardware/Architecture.
                              Session Title to Come
                                4:10pm - 4:30pm20 mins
                                Hardware/Architecture
                                Andes RISC-V Processor Solutions: From MCU to Datacenters
                                • Charlie Su - CTO and SVP of R&D, Andes Technology Corporation
                                4:40pm - 5:00pm20 mins
                                Hardware/Architecture
                                Ara 2.0: 64-bit RISC-V Vector Processor in 22nm FD-SOI
                                • Matheus Cavalcante - PhD Student, ETH Zurich
                                4:40pm - 5:00pm20 mins
                                Hardware/Architecture.
                                Session Title to Come
                                  4:40pm - 5:00pm20 mins
                                  Security/Verification
                                  Verifying RISC-V Vector and Bit Manipulation Extensions using STING Design Verification Tool
                                  • Shubhodeep Choudhury - CEO, Valtrix
                                  5:10pm - 5:30pm20 mins
                                  Hardware/Architecture.
                                  SafeRV: Building Blocks for Safety Critical RISC-V Systems
                                  • Neel Gala - CTO, InCore Semiconductors Pvt. Ltd.
                                  • Daniel Gracia Pérez - Software Domain Engineer (Critical Embedded Systems), Thales
                                  5:10pm - 5:30pm20 mins
                                  Security/Verification
                                  An Efficient Runtime Validation Framework based on the Theory of Refinement
                                  • Mitesh Jain - Staff R&D Engineer, Synopsys Inc
                                  • Pete Manolios - Professor, Northeastern University
                                  5:10pm - 5:30pm20 mins
                                  Hardware/Architecture
                                  Prototyping RISC-V Based Heterogeneous Systems-on-Chip with the ESP Open-Source Platform
                                  • Luca Carloni - Professor, Columbia University
                                  Tuesday, December 10
                                  NextThursday, December 12
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