Location: 1st Floor, Exhibit Hall A-1

Location: 1st Floor, Exhibit Hall A-1

Location: 1st Floor, Exhibit Hall A-1

Big Data and Fast Data applications are transforming enterprise environments involving core activities on-premises and on hyper-scale cloud infrastructure, as well as those that occur at the network’s edge, with new hubs or “data depots” emerging to address the locality and speed of access to data. Regional, local and remote data centers, and/or points of data aggregation, now provide opportunities to transform and add value to data as it flows from IoT and other edge applications, into the core of the network where it can be processed and analyzed to deliver actionable insights and value. Each of these data depots will require unique compute architectures and advanced data processing requirements paving the way for RISC-V -- an open instruction set architecture (ISA) designed to meet the diverse application needs of Big Data and Fast Data in this data-centric world. In this keynote, Western Digital CTO Martin Fink will discuss the value of purpose-built compute architectures and how RISC-V will enable a diversity of Big Data and Fast Data applications and workloads at each point along the spectrum, from edge to core.

Location: 1st Floor, Exhibit Hall A-1

Location: 1st Floor, Exhibit Hall A-2 & A-3

Don't miss out on the RISC-V Linux Hackathon, happening Dec. 4-5 on the Expo Floor at the RISC-V Summit.

Watch as a team of 10 expert hackers create cutting edge applications on a soft RISC-V CPU running Linux on the low-cost Avalanche FPGA board. 

Location: 1st Floor, Exhibit Hall A-1

Location: 1st Floor, Exhibit Hall A-2 & A-3

Location: 2nd Floor Meeting Rooms 203/204

Implementing an effective debugging system is crucial for efficient software development, and supporting a new bare metal multicore system in a debugger requires careful design and implementation choices. These choices depend on the programming and memory models of the target system -- there is no one-size-fits-all solution. In this discussion session, we outline the options and how they map onto targets with different characteristics. The GNU Debugger (GDB) and the Open On-Chip Debugger (OpenOCD) support RISC-V targets, but requires customization for each new multicore target. It is relatively straightforward to decide if, and which of, the single-inferior options are appropriate. For multi-inferior, if the target has in practice either a fully-shared or fully-disjoint address space for each core, then the single- or multiple-address space options are appropriate. Most implementations have a mix of the two. We implemented GDB and a GDBServer for a 36-core RISC-V system. For this scenario, multiple inferiors was an appropriate choice. On top of this, we implement hosted IO for each core. By freeing-up hardware engineers from learning "how to" hack on GDB absorbing precious engineering time it increases output from hardware engineers whilst delivering optimal product outcomes.

Don't miss out on the RISC-V Linux Hackathon, happening Dec. 4-5 on the Expo Floor at the RISC-V Summit.

Watch as a team of 10 expert hackers create cutting edge applications on a soft RISC-V CPU running Linux on the low-cost Avalanche FPGA board. Thanks to Western Digital for organizing!

Location: 2nd Floor Meeting Rooms 203/204

RISC-V Instruction Set Architecture has become a key driver for driving open source projects across wide gamut of end applications. Most recently we have seen a lot of application in the Internet of Things (IoT) segment, microcontrollers for a variety of traditional embedded applications, and applications requiring capability for low power operation of inference engines based on artificial neural networks. 

In Western Digital, we have developed super-scalar (2-way) 9-stage pipeline mostly in-order, open-source core ECHX1, targeting in-house embedded Storage System on Chip (applications). In this paper, we plan to present some of the architectural details of the core, and challenges in the implementations, as well as discuss application of the core for the Flash controller. Additionally, we will explain the vision for expansion of RISC-V cores into datacenter and enterprise market. 

We believe that open interface architectures will be key drivers of datacenter applications in 2023. We are witnessing computation shifting to dedicated machine learning and inference accelerators (also based on RISC-V Cores!) , and fast data migrating to large low latency, persistent memory pools. In this new world, the main processor interface connectivity capabilities, in particular bandwidth, latency and cache coherence capability for efficient memory sharing are becoming more relevant than raw compute capability of the cores. 

We will discuss open interfaces for persistent memories, such as JEDEC-standardized NVDIMM-P (Non-volatile dual inline memory module for persistent memories), and also exporting cache-coherence protocols (such as Tilelink) over ubiquitous fabrics such as Ethernet. We plan to discuss details of the MPF4brik – memory protocol fabrik, which exposes Tilelink on the Ethernet, and allows smart switching using P4-based programmable networking. We are envisioning low-cost SMP (symmetric multiprocessing) architectures based on open standards, which will enable hyperconvergence of processing and memory in the future datacenter.

Location: 1st Floor, Exhibit Hall A-1

Linux based embedded systems may need to execute real-time tasks from time to time. A Linux based motor control solution is a good example of such a system. While Linux may offer a rich execution environment, it is not practical to control motors in real time. This presentation will compare and contrast various solutions to this problem such as Overwhelming the Linux system with bandwidth, Adding a real-time controller to the system, and Provisioning an AMP capable SoC with deterministic L2 cache.

Location: 2nd Floor Meeting Room 209/210

2018 saw the rapid proliferation of the RISC-V architecture with commercial deployments of SiFive Core IP ranging from consumer wearables to enterprise cores. Modern compute workloads are evolving and require the ability to scale performance on-demand and very often have real-time, deterministic requirements. Intelligence is moving from the enterprise core to the IoT edge and requires a diverse combination of compute, storage and acceleration.

SiFive Core IP is architected to enable heterogeneous compute and efficiency requirements of applications by providing a scalable portfolio of CPU IP which can be customized according to the application requirements. In this talk we will highlight SiFive’s IP portfolio and how it embeds intelligent processing for a hyper-connected world of a trillion connected devices.

Location: 1st Floor, Exhibit Hall A-2 & A-3

Location: 2nd Floor Meeting Room 203/204

AI has been evolving at an unprecedented speed for the past 2 years. To enhance AI on the edge, BITMAIN’s Sophon Edge AI platform is not only equipped with 1TOP int8 computing power but also contains a RISC-V processor as the sensor hub connecting the outside world. We believe this unique platform will bring in many exciting and innovative applications to the AIOT space and continue to push forward the development of the greater RISC-V architecture.

Location: 1st Floor, Exhibit Hall A-1

In this talk, we introduce an open-source RISC-V-based SoC platform for edge inference applications based on NVIDIA Deep Learning Accelerator (NVDLA), NVIDIA's open-source inference engine, and SiFive's Freedom platform. NVIDIA has open-sourced its NVDLA initiative to address the computational demands of inference. NVIDIA's latest automotive SoC, Xavier, has incorporated two instances of the NVDLA. SiFive has open-sourced its Freedom platform, based on the RISC-V ISA, to quickly and cost effectively customize and add features for individual customers, unleashing the flexibility and power of custom silicon to the smallest company, inventor, and maker. SiFive has built FE310 and FU540 SoCs based on the Freedom platform, and has released HiFive1 and HiFive Unleashed development boards. NVIDIA and SiFive will jointly demo the NVDLA on the Freedom platform, and show the capabilities of the open-source edge inference platform.

Location: 2nd Floor Meeting Rooms 209/210

We present R&D in creating new formal verification tools to support hardware design languages, and Bluespec SystemVerilog in particular. We focus on "Secret Ninja Formal Methods": creating powerful formal tools that behave like compilers usable by normal engineers. Our tools perform static reasoning about user-defined properties of designs and implementations, in all environments, under arbitrary conditions. They are also able to reason about software, firmware, and hardware within the same framework, and thereby provide a system-wide assurance case. Finally, and perhaps most critically, our tools are completely transparent and can provide evidence, both mathematical and practical -- a sharp contrast to the "formal" tools available in the EDA market today. In our talk, we will also provide some technical details about the core of our tools, highlight their strengths and weaknesses, and review several case studies.

Location: 2nd Floor Meeting Rooms 203/204

The complexity of chips has rapidly increased in line with the predictions of Moore's law. Recent years have seen an explosion in the cost and time require to design advanced System-on-Chips (SoCs), systems-in-packages (SiPs), and PCBs. DARPA is addressing these challenges through two new electronic design automation (EDA) research programs: the Intelligent Design of Electronic Assets (IDEA) program and the Posh Open Source Hardware (POSH) program. These programs seek to form the foundation of an intelligent hardware compiler. The aim of these research efforts is to create a universal hardware compiler capable of automatically generating production ready GDSII drawings directly from source code and schematics -- essentially developing the equivalent of a software compiler. Achieving this ambitious goal will require advancing the state of the art in machine learning, optimization algorithms, and expert systems. This talk will provide an overview of the recently announced DARPA POSH and IDEA research programs and present economic and societal disruption enabled by an open source SoC design ecosystem and no human in the loop silicon compilers.

Location: 1st Floor, Exhibit Hall A-1

The current interest in high-performance machine-learning processors has led to a demand for very high-bandwidth memory systems and high-speed chip-chip communication links. We have developed a RISC-V-based AI platform including RISC-V cores with vector extensions, HBM2 high-bandwidth memory interfaces, and Interlaken chip-chip interconnects carrying the TileLink coherence protocol. The HBM2 and 56Gb/s SerDes interfaces are silicon-proven in a 16nm FinFET technology demonstrator, with upcoming support for next-generation nodes. The platform can be configured with a variety of RISC-V management and compute cores, optimized on-chip cache and scratchpad memory systems, and customer-specific hardware acceleration blocks, and is supported with a full system software stack.

Location: 2nd Floor Meeting Rooms 209/210

Cryptospec is an isolated trust module macrocell deeply embedded in 64-bit RISC-V system. Cryptospec protects sensitive information from unauthorized access. Its EEPROM/Flash/OTP serves as a storage for long-term, permanent keys such as RSA/DSA/ECDSA private keys as well as 3DES/AES/HMAC keys. Short-term keys such as TLS session keys 3DES/AES/HMAC keys are stored in RAM, and privacy related information in EEPROM/Flash. It prevents running unauthorized software based on go-or-no-go decision to CPU based on trust measure of the executing instructions/data. It also protects communication with outside world. Cryptospec has its own SSL/TLS or other secure communication mechanism which can exist in parallel with ones running on RISC-V system. Cryptospec OS runs on Cryptospec hardware offering two APIs, a packet API which enables outside on-chip CPUs to talk to Cryptospec, and another API which user download applets can link to. 

Compared to prior secure elements with 1-bit serial interface, Cryptospec's hardware interface with RISC-V Coreplex configured to fit RISC-V coreplex system bus. Cryptospec can invoke interrupts for each of RISC-V cores. RISC-V cores can invoke Cryptospec interrupt. Cryptospec library includes plethora of asymmetric can symmetric cryptographic functions, which can be securely linked to user applets downloaded, and used by Cryptospec's encrypted download, communication, and system functions. Cryptospec will be fabricated along with quadcore bi-endian 64-bit RISC-V coreplex system and is certificable at the level of FIPS140-2 Level 3 federal government procurement standard. Cryptospec contains two 32-bit SH-2 MCUs with 2-stage pipeline with compact critical timing paths.

Location: 2nd Floor Meeting Rooms 203/204

The momentum of the RISC-V ecosystem has spawned an increasing number of complex RISC-V processors by both commercial companies and the open source community. As these processor core designs grow in complexity, verification will continue to be the key challenge to delivering RISC-V processors that have robust functionality and meet target performance. In the open-source world, riscv-tests and riscv-torture have been widely used to verify RISC-V processors. These tests provide the necessary foundation to verify compliance to the ISA, but are not sufficient to address the verification challenges of complex processors. 

In this session, we propose a comprehensive RISC-V verification platform (RISCV-VP) built with industry standard SystemVerilog (SV) and Universal Verification Methodology (UVM). The core of RISCV-VP is a SV/UVM-based random RISC-V assembly instruction generator, which supports many advanced features including full RISC-V privileged mode, page table randomization, page fault injection, nested loop structures, large numbers of sub-programs, CSR testing, and MMU stress testing. This instruction generator currently supports RV32IMC and RV64IMC subsets of the ISA. It can be easily extended to support other RISC-V instruction extensions. In addition to the instruction generator, RISCV-VP also provides useful components such as an interrupt agent, a debug agent, and a functional coverage monitor. We tested three open source RISC-V processors with RISCV-VP,  ETH's RI5CY, Ariane plus a third 32b core. We present results that show how easily this framework integrates these processors and achieves much higher code and functional coverage compared with other open source verification flows. The framework found numerous bugs in the designs tested that were not found with other in-house or open-source verification flows, including in both datapath and control units.

Location: 1st Floor, Exhibit Hall A-1

This talk describes the architecture and implementation of Hwacha, a scalable data-parallel accelerator focused on improving energy efficiency while remaining a favorable compiler target. Inspired by classical vector machines such as the Cray-1, as well as lessons learned from our previous vector-thread architectures Scale and Maven, Hwacha introduces the vector-fetch architectural paradigm: Vector instructions are hoisted into a separate thread to enable more aggressive access/execute decoupling of the vector data stream. Hwacha has been developed as a RISC-V non-standard extension (ISA string Xhwacha) block that attaches to the RoCC (Rocket Custom Coprocessor) interface. Several VLSI implementations have been taped-out in 16 nm, 28 nm, and 45 nm technology nodes at 1 GHz+ clock frequencies. Preceding this talk will be the open-source release of the ver- sion 4 RTL, compiler toolchain, and simulation and verification infrastructure, including FireSim AWS FPGA integration. Future iterations will transition to the proposed RISC-V V extension and feature 2D vector support based on vtype polymorphism.

Location: 2nd Floor Meeting Rooms 209/210

In this session, we discuss our work to develop a parameterized set of modules for design space exploration for RISC-V ISA based architectures. We introduce a design tool with:

• Multiple RISC-V cores with different levels of complexity (e.g., single-cycle core, multiple-cycle, and reconfigurable pipelined)
• A programmable memory system with reconfigurable multilevel cache subsystems
• A flexible interconnect network supporting programmable topology, router size and routing algorithm. 

The aim of this work is to provide an easy to use, open-source, parameterized, fully synthesizable platform for students and researchers experimenting with the RISC-V ISA features to quickly bring up a complete and fully working architecture and start applying their own modifications.

Don't miss out on the RISC-V Linux Hackathon, happening Dec. 4-5 on the Expo Floor at the RISC-V Summit.

Watch as a team of 10 expert hackers create cutting edge applications on a soft RISC-V CPU running Linux on the low-cost Avalanche FPGA board. Thanks to Western Digital for organizing!

Location: 2nd Floor Meeting Rooms 203/204

The Physical Memory Protection (PMP) available on RISC-V cores is hardware that limits the access to memory and peripheral devices to only the code that needs to access those resources. The PMP allows an application developer to create more robust, safe and secure applications. The application can be organized by processes, each having access to its own memory and peripheral space. Not only does the PMP prevent application code from accessing memory or peripheral devices outside its designated area but, it can also be used to detect stack overflows. In this lecture, we will show how the PMP can interact with an RTOS and what recourses an RTOS has when a memory or I/O access violation is detected.

Location: 1st Floor, Exhibit Hall A-1

RISC-V is gaining substantial market traction; in the process the ecosystem's focus is moving from purely legacy/incumbent processor-centric thinking to system-level issues. Part of that move is a growing realization that many, if not most, designs will include RISC-V, in addition to other CPUs and GPUs, rather than as a system-wide substitute. Issues of heterogeneous design, therefore become key architectural considerations. In addition there needs to be an infrastructure that supports the co-existence of legacy subsystems with new ones such as those implemented using RISCV. An "ecosystem on chip" should be developed as system: not as though it were a collection of independent pieces. This presentation will look at these issues and how they can be addressed. We will provide specific examples, focusing particularly on designs that combine RISC-V and Arm processors within the same SoC.

Location: 2nd Floor Meeting Rooms 209/210

In this session industry veteran Cesare Garlati, long time supporter of the RISC-V Foundation and active member of the RISC-V Security Group, will share the latest on RISC-V security and will offer his practitioner advice for developing secure applications. Garlati will start with an explanation of the security building blocks defined by the ISA including privileged modes and physical memory protection. He will then show how to combine these blocks to develop trusted applications with particular emphasis on IoT devices that lack MMU – and this is where the audience will be surely impressed with the capabilities of RISC-V. Finally, Garlati will introduce a breakthrough system design philosophy, entirely based on free and open standards, that allows hardware-enforced software-defined separation of data, programs and peripherals for an unlimited number of trusted execution environments. This session will appeal to anyone with an interest in embedded security in general and in RISC-V in particular: from SoC designers to hardware and software architects to OEMs and system integrators.In this session industry veteran Cesare Garlati, long time supporter of the RISC-V Foundation and active member of the RISC-V Security Group, will share the latest on RISC-V security and will offer his practitioner advice for developing secure applications. Garlati will start with an explanation of the security building blocks defined by the ISA including privileged modes and physical memory protection. He will then show how to combine these blocks to develop trusted applications with particular emphasis on IoT devices that lack MMU – and this is where the audience will be surely impressed with the capabilities of RISC-V. Finally, Garlati will introduce a breakthrough system design philosophy, entirely based on free and open standards, that allows hardware-enforced software-defined separation of data, programs and peripherals for an unlimited number of trusted execution environments. This session will appeal to anyone with an interest in embedded security in general and in RISC-V in particular: from SoC designers to hardware and software architects to OEMs and system integrators.

Location: 2nd Floor Meeting Rooms 203/204

As the RISC-V ISA specification evolves and adds an ever-increasing number of optional architecture extensions, a processor design methodology that allows for both rapid architectural exploration and simplified creation of easily implementable RTL becomes essential. What is needed is a high-level processor description language optimized for RISC-V. The presentation will demonstrate how the new and enhanced Codasip Studio 8 was used to (a) create a new 64-bit RISC-V processor implementation and (b) to perform design exploration around the emerging B and P standard extensions. Additionally, it will introduce the following new Studio and software tool functionality: 

• Support for LLVM debugger (LLDB) and OpenOCD 
• LLVM 7.0 
• Studio/CodeSpace IDEs based on Eclipse Oxygen, along with more interactive consoles 
• Improved test suites and verification to better support user-defined RISC-V extensions.

Location: 1st Floor, Exhibit Hall A-1

There are myriad architectures for multiple core processing systems and their memories, which vary greatly and are highly tuned to the application. In the past such systems have had bespoke processors or standard processors shoe-horned in. The advent of an open processor instruction set architecture in RISC-V provides an exciting new opportunity to address a broad range of embedded processing applications with tailored optimizations and instruction customizations. 

A major differentiation between architectures will be in the memory hierarchy and capabilities; general purpose processors drive toward coherent caches to maximize CPU performance using temporal locality; DSPs stream data; GPUs have texture caches and separate processor memories. In some processing applications, it is beneficial to have a transactional memory hierarchy, with high bulk bandwidth and a lot of support in the memories for operations such as "look up a value and add it to a table". Such operations do not necessarily marry well to a load/store CPU architecture, and the performance of a system will tend to be limited by the number of memory transactions per second as well as CPU cycles; this latter issue encourages memory-centric processing, and hence the latency for transactions from a processor may be high (perhaps even over a hundred cycles). To cover this latency and achieve high silicon efficiency requires a lot of CPU threads, and suitable sharing of CPU resources. 

In this talk, we discuss some of the background, and describe the example of a thousand RISC-V harts performing the processing required in a SmartNIC. We show how a RISC-V solution can be tailored with a suitable choice of instruction set features, privilege modes and debug methodology; we cover at a high level the organization of memories and RISC-V harts that provides efficient processing with high latency memory transactions; we look at the instruction set customizations that allow this to handle RISC-V hart interaction with the memory systems and other harts; and we show how this applies in an example.

Location: 2nd Floor Meeting Rooms 209/210

The RISC-V ISA defines some key building blocks for secure computing including privileged modes and crypto extensions. However, commercial implementations may not include these standard extensions or provide vendor-specific architectures requiring additional non-standard specialized hardware. For system designers, security is seldom a differentiating feature and often added late in the development cycle to a predefined architecture. History shows that many security implementations fail due to an excess of complexity and an inability to verify the fully integrated solution – when they fail, there is a real risk that the blame will affect the RISC-V brand as a whole rather than the specific faulty implementation.

As RISC-V commercialization proceeds, many aspects of its ecosystem are now “Ready for Business” but there has not been a discussion of the commercial readiness of the security segment. This enlightening panel will cover the RISC-V security issues faced by a customer during implementation, discuss several commercial solutions to secure RISC-V and cover holistic test & verification best practices at the platform level.

Location: 1st Floor, Exhibit Hall A-2 & A-3

Location: 2nd Floor Meeting Rooms 203/204

Universal availability of mainstream Linux-capable SoCs is a major milestone for RISC-V. A multi-core, Linux-capable RISC-V SoC will be unveiled at the Summit, the first mainstream, widely available, powerful and flexible RISC-V SoC product from a major vendor. To get the platform into the hands of developers worldwide without limitations, support for the SoC was developed by Antmicro in the free and open source Renode framework. This includes not only the CPU but the entire SoC, also providing the possibility to connect external elements like virtual sensors as well as other SoCs/boards, allowing users to simulate production software for their products while waiting for silicon to be available. Additional collaboration features of Renode, its integration with continuous integration and testing frameworks will further enhance this revolutionary simulator-first workflow that will be described in this presentation.

Location: 1st Floor, Exhibit Hall A-1

With the vast amount of data being generated and stored on SSD, the limited network bandwidth is the bottleneck for processing this data. Therefore, compute must move closer to where the data resides. In this talk, we will show how Eideticom's NoLoad NVMe accelerators running on SiFive's RISC-V platforms enable a seamless method for running your applications directly on the storage server, with minimal impact on the host CPU and network resources.

Location: 1st Floor, Exhibit Hall A-1

PULP is a silicon-proven open-source parallel platform for ultra-low power computing created by researchers at ETHZ and UNIBO with the objective of delivering high compute bandwidth combined with high energy efficiency. The platform is organized in clusters of RISC-V cores that share a common and tightly-coupled data memory subsystem. The platform also includes a set of System Verilog-described IP blocks, their related synthesis and simulation scripts, and the runtime software (written in C and RISC-V assembly) necessary to provide a complete system. All of the architecture, IP, scripts and software are open sourced to encourage global collaboration and development. 

Integrating eFPGA technology with the PULP Platform enables users to offload critical functions from the processor(s) and implement them in eFPGA fabric. This approach enables the creation of multiple hardware co-processors that increase system efficiency and performance while decreasing power consumption. An example use case for the eFPGA technology is to enable hardware acceleration of feature extraction for AI applications. In this case, using eFPGA fabric significantly improves performance and lowers power consumption by offloading those functions from the RISC-V processor while still maintaining the ability to adopt and implement new algorithms even after field development. Our goal is to implement AI at the edge in a single platform with reconfigurable acceleration capabilities; for this purpose, ETH and QuickLogic are developing a test chip in 22FDX technology which will showcase the benefits of having AI feature extraction implemented in eFPGA fabric to achieve higher performance with the lowest possible power consumption.

Location: 2nd Floor Meeting Rooms 209/210

Security has emerged as the preeminent concern in architecting and designing Embedded Systems in broad deployment today for mission critical applications, where higher levels of reliability and tamper-resistance are fundamental requirements. The process of booting Linux on an SOC involves multiple stages before transferring control to the Linux Kernel. After Reset is applied, a First Stage Boot Loader (FSBL) pointed to by the Reset Vector is invoked. FSBL is typically stored in on-chip NVM which is protected by a few layers of security restricting access privileges. As the methods of attack are becoming more sophisticated, this approach is deemed inadequate to guard against a scenario where a malicious agent manages to alter the FSBL. We present here Secure Boot of SOC advanced security capabilities: Before the FSBL is executed, a “Zero Stage Boot Loader” (ZSBL) is pushed into the SOC by the “Root of Trust” for the purpose of authenticating the NVM image before transferring control to FSBL. A Secure Hash Algorithm (SHA) of NVM image is run on the RV64G cores included in the SOC. The calculated hash is then checked against a purported value in a signed code certificate for FSBL. Choice of SHA512/256 was made to take advantage of 64-bit compute and managed to speed up the operation by partitioning the workload over 2 Cores.

Don't miss out on the RISC-V Linux Hackathon, happening Dec. 4-5 on the Expo Floor at the RISC-V Summit.

Watch as a team of 10 expert hackers create cutting edge applications on a soft RISC-V CPU running Linux on the low-cost Avalanche FPGA board. Thanks to Western Digital for organizing!

Location: 1st Floor, Exhibit Hall A-1

Extensibility is in integral part of the RISC-V Instruction Set Architecture (ISA). The decision to extend the ISA in a particular way is mostly influenced by few highly structuring hypotheses rooted in the application domain(s) for which a performance boost is required. The motivation for such a boost can be faster execution but it can also at same time be directed towards reducing power consumption. 

One of the challenges posed by extensions is how to preserve balanced characteristics of the micro architecture used: gate cost, critical paths, ... GAP8 leverages the PULP open source initiative which is itself using the RISC-V ISA for its processing elements. Both PULP and GAP8 are heavily using RISC-V extensions. 

In this session, we will show how these extensions are bringing a significant performance/energy boost compared to the base RISC-V ISA for Deep/Convolutional Neural Network (DNN/CNN) applications by combining Digital Signal Processing (DSP) related extensions with advanced Single Instruction Multiple Data (SIMD) capability. We will go step by step through the optimization process that led to the ISA extension definition. We will then show how such an extended core can be used efficiently in a multiple core shared memory model still using CNN/DNN applications as a driving use case. We will illustrate the capability of the GAP8 multiple core SoC on some real-life medium complexity CNNs.

Location: 2nd Floor Meeting Rooms 209/210

ISO26262 is becoming very important for the semiconductor industry, as it is an entry requirement for many automotive and safety-critical applications which represent a massive opportunity for the RISC-V community. But the risk connected to the use of RISC-V is still regarded as high especially when used for a S/W intensive application. In this context, monitoring software execution and potential anomalies is increasingly important in order to address

• systematic faults in the design (software or hardware bugs) 
• run-time failure of the system
• deliberate interference 

This can be achieved with a minimum overhead (hardware and software) in a non-intrusive way and with easy instrumentation. This presentation will cover these fundamental concepts and discuss hardware and software FuSa features across the entire SoC.