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Informa
Key Sessions
Helena Handschuh
An Open Source Approach to System Security
Rambus
Stefan Dyckerhoff
How RISC-V made the Quick Jump from Academia to Industry and Why it will Change the Entire Semiconductor Industry - a Venture Capital perspective
Sutter Hill Ventures
Krste Asanovic
Keynote Panel: Opportunity and Risks in Open Source Hardware
UC Berkeley | SiFive
Randy Allen
RISC-V Software State of the Union
SiFive
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Wednesday, December 11

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Wednesday, December 11

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8:00am - 5:30pm570 mins
Registration
Registration
    9:00am - 9:05am5 mins
    Keynotes
    Welcome
      9:05am - 9:25am20 mins
      Keynotes
      RISC-V and Chips Alliance Address new Compute Requirements
      • Zvonimir Bandic - Sr. Director, Next Gen Platform Technologies | Chairman of the Board, CHIPS Alliance, Western Digital | CHIPS Alliance
      • Dejan Vucinic - Director, NVM Systems Architecture, Western Digital
      9:25am - 9:45am20 mins
      Keynotes
      An Open Source Approach to System Security
      • Helena Handschuh - Rambus Fellow & Chair, RISC-V Foundation Security Standing Committee, Rambus
      9:45am - 10:05am20 mins
      Keynotes
      How RISC-V made the Quick Jump from Academia to Industry and Why it will Change the Entire Semiconductor Industry - a Venture Capital perspective
      • Stefan Dyckerhoff - Managing Director, Sutter Hill Ventures
      10:05am - 10:25am20 mins
      Keynotes
      Open Source Processor IP for High Volume Production SoCs: CORE-V Family of RISC-V Cores
      • Rick O' Connor - Founder, President & CEO, OpenHW Group
      10:25am - 11:10am45 mins
      Keynotes
      Keynote Panel: Opportunity and Risks in Open Source Hardware
      • Krste Asanovic - Professor | Chief Architect, UC Berkeley | SiFive
      • Mendy Furmanek - IBM Director – OpenPOWER Processor Enablement; OpenPOWER President, IBM
      • Joseph Jacks - Founder and CEO, OSS Capital
      • Brandon Lewis - Editor-in-Chief, Open Systems Media
      • Tim Whitfield - VP Strategy Embedded and Automotive, ARM
      11:10am - 11:30am20 mins
      Keynotes
      Qualcomm Diamond Sponsor Session: Global Ambitions for RISC-V
      • Calista Redmond - CEO, RISC-V Foundation
      • Travis Lanier - Senior Director, Product Management, Qualcomm
      • Rob Oshana - VP Software Engineering, NXP
      • Yu Pu - IoT SOC Lead, Alibaba
      11:30am - 4:00pm270 mins
      Poster Gallery
      Poster Gallery on Expo Floor
      • Alfredo Arnaud - Dr.Eng, Professor, Universidad Católica del Uruguay
      • Sven Beyer - Product Manager Design Verification, OneSpin Solutions
      • Donato Kava - Associate Staff, MIT Lincoln Laboratory
      • Lee Moore - Lead Engineer, Imperas
      • Boris Shingarov - Senior Software Designer, Labware
      • Umesh Sisodia - SMTS, Circuitsutra Technologies Pvt Ltd
      • Francesco Vigli - Digital Hardware Designer, AizoOn Group
      • Adam Wiethuechter - Chief Scientist, Critical Technologic Inc.
      • Shaomin Xiong - Technologist, Western Digital
      • Atif Zafar - CEO, Pixilica
      11:30am - 12:50pm80 mins
      Networking
      Lunch Break
        11:30am - 4:00pm270 mins
        Expo
        Expo Hall
          12:50pm - 1:10pm20 mins
          Software
          RISC-V Software State of the Union
          • Randy Allen - VP, RISC-V Software, SiFive
          12:50pm - 1:10pm20 mins
          Security/Verification
          Formal Methods for Hardware-Software Integration on RISC-V Embedded Systems
          • Samuel Gruetter - PhD student in Computer Science, MIT
          12:50pm - 1:10pm20 mins
          Hardware/Architecture
          Enabling AI on Low Power Endpoint Devices Utilizing the QuickLogic and SiFive Freedom Aware Templates
          • Brian Faith - CEO, QuickLogic Corporation
          1:20pm - 1:40pm20 mins
          Software
          Production-ready RISC-V Support in LLVM/Clang 9.0 - How we Got There and What's Next
          • Alex Bradbury - Director, lowRISC CIC
          1:20pm - 1:40pm20 mins
          Hardware/Architecture.
          Ruby Sponsor SiFive presents: The SiFive Vector Processor
          • Mark Throndson - Senior Director of Product Management and Marketing, SiFive
          1:20pm - 1:40pm20 mins
          Hardware/Architecture
          RISC-V For Heterogeneous Computing
          • Justin Cormack - Security Lead, Docker
          1:50pm - 2:10pm20 mins
          Security/Verification.
          seL4 on RISC-V: Verified OS for True Security
          • Gernot Heiser - Professor UNSW Sydney and seL4 Evangelist, Data61, Data61 and UNSW Sydney
          1:50pm - 2:10pm20 mins
          Security/Verification
          Modeling a State Machine Security Monitor for RISC-V Architecture
          • Patrick Jungwirth - Computer Engineer, US Army Research Lab
          1:50pm - 2:10pm20 mins
          Hardware/Architecture
          SweRV Cores Roadmap
          • Zvonimir Bandic - Sr. Director, Next Gen Platform Technologies | Chairman of the Board, CHIPS Alliance, Western Digital | CHIPS Alliance
          • Robert Golla - Senior Fellow, Western Digital
          2:20pm - 3:10pm50 mins
          Hardware/Architecture
          Processor IP Showcase with Andes Technology, CHIPS Alliance, Codasip, Shakti Project, SiFive, Syntacore, OpenHW Group
          • Kevin Chen - Senior Architect, Andes Technology
          • Drew Barbier - Sr. Manager, SiFive Core IP Product Marketing, SiFive
          • Zvonimir Bandic - Sr. Director, Next Gen Platform Technologies | Chairman of the Board, CHIPS Alliance, Western Digital | CHIPS Alliance
          • Karel Masarik - CEO and Founder, Codasip
          • Arjun Menon - Senior Project Officer, IIT Madras | Shakti Project
          • Alexander Redkin - Executive Director, Co-Founder, Syntacore
          • Rick O' Connor - Founder, President & CEO, OpenHW Group
          • Gajinder Panesar - CTO, UltraSoC
          • Anand Joshi - Anlayst, Computer Vision & AI, Tractica
          2:20pm - 2:40pm20 mins
          Software
          Integrate RISC-V to build Open Common Automotive Platform
          • Tiejun Chen - Technical Leader and Staff Engineer, VMware
          2:20pm - 2:30pm10 mins
          Security/Verification
          RISC-V Enclaves: A Clean Slate Approach To Linux Security
          • Cesare Garlati - Co-Founder, Hex Five Security
          2:30pm - 2:40pm10 mins
          Security/Verification
          RISC-V: A New Zero-Trust Model for Cyber Resilient Avionics
          • Kevin Kinsella - System Architect, Northrop Grumman
          2:50pm - 3:10pm20 mins
          Security/Verification.
          OneSpin presents: More than the Core: Verifying RISC-V SoCs
          • Nicolae Tusinschi - Product Specialist Design Verification, OneSpin Solutions
          2:50pm - 3:00pm10 mins
          Security/Verification
          Different Trace Methods and Efficient Ways to Utilize Them
          • Thomas Andersson - Product Manager, IAR Systems
          • Robert Chyla - Lead Emulation Architect, IAR Systems
          3:00pm - 3:10pm10 mins
          Security/Verification
          Debugging on Homogeneous and Heterogeneous Multicore SoCs Containing a Mix of RISC-V and non-RISC-V Cores
          • Hugh O'Keeffe - Engineering Director, Ashling
          • Roisin O'Keeffe - VP, Business Enterprise, Ashling
          3:10pm - 3:40pm30 mins
          Networking
          Networking Break
            3:40pm - 4:00pm20 mins
            Software
            Headline Sponsor Western Digital presents: RISC-V Hypervisor Support
            • Alistair Francis - Principal System Engineer, Western Digital
            • Anup Patel - Technologist, Western Digital
            3:40pm - 4:00pm20 mins
            Security/Verification
            RISC-V Processor Verification based on Open-source Framework and State-of-the-art Cloud-based Methodologies
            • Lee Moore - Lead Engineer, Imperas
            • Richard Ho - Principal Hardware Engineer, Google
            3:40pm - 4:00pm20 mins
            Hardware/Architecture
            Innovation in CPU Architecture, Pushing Data from Edge to Cloud
            • Caffrey Chen - Chief Processor Architect, Alibaba
            4:10pm - 4:30pm20 mins
            Security/Verification
            Ruby Sponsor SiFive presents: Enabling Security with AWS Qualified IoT Devices
            • David Lee - Director of Product Management, SiFive
            4:10pm - 4:30pm20 mins
            Software
            Working Towards a Common C Library for Small RISC-V Systems
            • Keith Packard - Principal Engineer, SiFive
            4:10pm - 4:30pm20 mins
            Hardware/Architecture
            Andes RISC-V Processor Solutions: From MCU to Datacenters
            • Charlie Su - CTO and SVP of R&D, Andes Technology Corporation
            4:40pm - 5:00pm20 mins
            Security/Verification.
            Rambus presents: Challenges and Benefits of Certification for Security Hardware
            • Ben Levine - Senior Director, Product Management, Rambus
            4:40pm - 5:00pm20 mins
            Security/Verification
            Verifying RISC-V Vector and Bit Manipulation Extensions using STING Design Verification Tool
            • Shubhodeep Choudhury - CEO, Valtrix
            4:40pm - 5:00pm20 mins
            Hardware/Architecture
            Ara 2.0: 64-bit RISC-V Vector Processor in 22nm FD-SOI
            • Matheus Cavalcante - PhD Student, ETH Zurich
            5:10pm - 5:30pm20 mins
            Hardware/Architecture
            Prototyping RISC-V Based Heterogeneous Systems-on-Chip with the ESP Open-Source Platform
            • Luca Carloni - Professor, Columbia University
            5:10pm - 5:30pm20 mins
            Hardware/Architecture.
            SafeRV: Building Blocks for Safety Critical RISC-V Systems
            • Neel Gala - CTO, InCore Semiconductors Pvt. Ltd.
            • Bertrand Tavernier - VP Software Research & Technologies, Thales
            5:10pm - 5:30pm20 mins
            Security/Verification
            An Efficient Runtime Validation Framework based on the Theory of Refinement
            • Mitesh Jain - Staff R&D Engineer, Synopsys Inc
            Tuesday, December 10
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