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Wednesday, December 9, 2020 - PST (Pacific Standard Time, GMT-8)
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Wednesday, December 9, 2020 - PST (Pacific Standard Time, GMT-8)
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Streams
9:00am - 9:05am5 mins
Keynotes
RISC-V International Awards 2020
- Krste Asanovic - Professor | Chief Architect, UC Berkeley | SiFive
- Mark Himelstein - CTO, RISC-V International
9:05am - 9:20am15 mins
Keynotes
RISC-V: The Next Ten Years
- Krste Asanovic - Professor | Chief Architect, UC Berkeley | SiFive
9:20am - 9:35am15 mins
Keynotes
CORE-V: Industrial Grade Open Source RISC-V Cores
- Rick O'Connor - President & CEO, OpenHW Group
9:35am - 10:05am30 mins
Keynotes
Is RISC-V Verification Ecosystem Ready for the Coming Innovation Tsunami?
- Ann Mutschler - Executive Editor/EDA, Semiconductor Engineering
- Simon Davidmann - President & CEO, Imperas Software Ltd
- Steve Richmond - Design Verification Manager for the Central R&D Division, Silicon Labs
- Mike Thompson - Director of Verification Engineering, OpenHW Group
- Nasr Ullah - Senior Director, Performance Architecture, SiFive
10:05am - 10:35am30 mins
Keynotes
Fireside Chat with the architects of RISC-V
- Nitin Dahad - Editor-in-Chief, embedded.com
- David Patterson - Vice Chair, RISC-V International
- Chris Lattner - President, Product and Engineering, SiFive
- Krste Asanovic - Professor | Chief Architect, UC Berkeley | SiFive
10:30am - 11:00am30 mins
Meet the Speakers: Room A
LIVE Q&A Forum with the Keynote Speakers
11:00am - 11:20am20 mins
Security & Functional Safety
Migrating to RISC-V while maintaining TrustZone Compatibility
- Dany Nativel - Security Director, SiFive
11:00am - 11:20am20 mins
System Architectures
RISC-V & SoC Architectural Exploration for AI and ML accelerators
- Simon Davidmann - President & CEO, Imperas Software Ltd
- Duncan Graham - Senior Applications Engineer, Imperas Software Ltd.
11:00am - 11:20am20 mins
Verification
Closing the RISC-V Compliance Gap via Fuzzing
- Vladimir Herdt - Senior Researcher, University of Bremen / DFKI GmbH
11:20am - 11:30am10 mins
Tech Talk
Tech Talk with Cobham Gaisler: The Case for RISC-V in Space Applications
- Jan Andersson - Director of Engineering, Cobham Gaisler
11:30am - 11:50am20 mins
Security & Functional Safety
Time Protection: Preventing Microarchitectural Timing Channels on RISC-V
- Nils Wistoff - Ph.D. Student, ETH Zurich
11:30am - 11:50am20 mins
System Architectures
Cluster CPU -- New Micro-architecture for Cluster Computing
- Sean Halle - CEO, Intensivate
11:30am - 11:50am20 mins
Verification
Coverage-driven Formal Verification for RISC-V ISA Compliance
- Ashish Darbari - CEO, AXIOMISE
11:50am - 12:00pm10 mins
Tech Talk
Tech Talk with Seagate: Data on the Move: A RISC-V Opportunity
- Bruno Masson - Director, Lyve Product Management, Seagate
12:00pm - 12:20pm20 mins
Security & Functional Safety
Coco: Co-Design and Co-Verification of Masked Software Implementations on CPUs
- Barbara Gigerl - PhD Student, Technical University of Graz
12:00pm - 12:20pm20 mins
Software & Tools
Enabling open programming models in RISC-V for AI and HPC
- Andrew Richards - Founder | CEO, Codeplay Software Ltd
12:00pm - 12:20pm20 mins
System Architectures
Building an Open Control Stack for Quantum Computers using RISC-V Ecosystem
- Anastasiia Butko - Research Scientist, LBNL
12:00pm - 12:20pm20 mins
Verification
Enhancing Verification Coverage for RISC-V Vector Extension Using RISCV-DV
- DingKai Huang - Engineering Manager, Andes Technology
- Tao Liu - Senior Hardware Engineer, Google
12:20pm - 12:30pm10 mins
Tech Talk
Tech Talk with Lauterbach: Debug and Trace of RISC-V based SOC
- Dennis Griffith - Field Application Engineer, Lauterbach
12:30pm - 12:50pm20 mins
Community Ecosystem
Building a RISC-V Ecosystem
- Yunsup Lee - Co-founder and CTO, SiFive
12:30pm - 12:50pm20 mins
Hardware Cores/SoCs
Developing with PolarFire® SoC
- Hugh Breslin - Design Engineer, Microchip
12:30pm - 12:50pm20 mins
Security & Functional Safety
Educating the Computer Architects of Tomorrow's Critical Systems with RISC-V
- Leonidas Kosmidis - Senior Researcher and Junior Faculty, Barcelona Supercomputing Center (BSC) and Polytechnic University of Catalonia (UPC)
12:30pm - 12:50pm20 mins
System Architectures
OmniXtend: Open Source Cache-coherence over Ethernet
- Zvonimir Bandic - Sr. Director, Next Gen Platform Technologies | Chairman of the Board, CHIPS Alliance, Western Digital | CHIPS Alliance
12:50pm - 1:30pm40 mins
Meet the Speakers: Room A
LIVE Q&A Forum with Speakers: Room A
- Dany Nativel - Security Director, SiFive
- Nils Wistoff - Ph.D. Student, ETH Zurich
- Barbara Gigerl - PhD Student, Technical University of Graz
- Leonidas Kosmidis - Senior Researcher and Junior Faculty, Barcelona Supercomputing Center (BSC) and Polytechnic University of Catalonia (UPC)
- Vladimir Herdt - Senior Researcher, University of Bremen / DFKI GmbH
- Ashish Darbari - CEO, AXIOMISE
- DingKai Huang - Engineering Manager, Andes Technology
- Hugh Breslin - Design Engineer, Microchip
12:50pm - 1:30pm40 mins
Meet the Speakers: Room B
LIVE Q&A Forum with Speakers: Room B
- Andrew Richards - Founder | CEO, Codeplay Software Ltd
- Zvonimir Bandic - Sr. Director, Next Gen Platform Technologies | Chairman of the Board, CHIPS Alliance, Western Digital | CHIPS Alliance
- Anastasiia Butko - Research Scientist, LBNL
- Sean Halle - CEO, Intensivate
- Simon Davidmann - President & CEO, Imperas Software Ltd
- Yunsup Lee - Co-founder and CTO, SiFive
1:00pm - 1:20pm20 mins
Software & Tools
Porting Tock to OpenTitan
- Alistair Francis - Technologist, R&D Engineering, Western Digital
1:30pm - 1:50pm20 mins
Hardware Cores/SoCs
RISC-V in 5G New Radio Small Cell Base Stations
- Gajinder Panesar - Fellow, Mentor, A Siemens Business
- Peter Claydon - President, Picocom
1:30pm - 1:50pm20 mins
Security & Functional Safety
Secure IoT Firmware for RISC-V
- Cesare Garlati - Founder, Hex Five Security
- Sandro Pinto - Research Scientist and Professor, Universidade do Minho
1:30pm - 1:50pm20 mins
Software & Tools
A Complete no-human-in-the-loop Open-Source "Idea to Manufacturing" SoC Compiler
- Mohamed Shalan - Associate Professor at the Department of Computer Science and Engineering, The American University, Cairo
1:50pm - 2:00pm10 mins
Tech Talk
Tech Talk with SmartDV: SmartDV’s RISC-V Solutions
- Bipul Talukdar - Director - Applications Engineering, North America, SmartDV Technologies
2:00pm - 2:20pm20 mins
Hardware Cores/SoCs
Ziptilion™: Boosting RISC-V with An Efficient and O/S Transparent Memory Compression System
- Angelos Arelakis - Chief Technology Officer, ZeroPoint Technologies AB
2:00pm - 2:20pm20 mins
Software & Tools
Software "PPA" Metrics: More Results from Real-World Applications
- Joe Circello - Technical Fellow, Chief Engineer, NXP Semiconductors, N.V.
2:00pm - 2:20pm20 mins
System Architectures
Codasip Application Class RISC-V Processor Solutions
- Zdeněk Přikryl - CTO, Codasip
2:20pm - 2:30pm10 mins
Tech Talk
Tech Talk with GigaDevice: GD32VF103 A RISC-V based MCU
- Reuben Townsend - EMEA FAE Manager, GigaDevice Semiconductor Ltd
2:30pm - 2:50pm20 mins
Hardware Cores/SoCs
SemiDynamics new family of High Bandwidth Vector-capable Cores
- Roger Espasa - CEO, SemiDynamics Technology Services
2:30pm - 2:50pm20 mins
Security & Functional Safety
Building a Secure Platform with the Enhanced IOPMP
- Paul Shan-Chyun Ku - Deputy Technical Director of Architecture Division, Andes Technology
2:30pm - 2:50pm20 mins
Software & Tools
seL4 on RISC-V: Fast, Secure, Open-source and Proved Bug-free OS Kernel
- Gernot Heiser - Professor UNSW Sydney and seL4 Evangelist, Data61, Data61 and UNSW Sydney
2:50pm - 3:00pm10 mins
Tech Talk
Tech Talk with Antmicro: Building your world out of blocks with Renode and LiteX
- Piotr Zierhoffer - Engineering Manager, Antmicro
3:00pm - 3:20pm20 mins
Community Ecosystem
The State of Cloud Applications and Containers for RISC-V
- Carlos Eduardo de Paula - Cloud Architect, Red Hat
3:00pm - 3:20pm20 mins
Hardware Cores/SoCs
Fueling the Datasphere: How RISC-V Enables the Storage Ecosystem
- Richard Bohn - Director of RISC-V Core Development, Seagate Technology
3:00pm - 3:20pm20 mins
Software & Tools
AndesClarity: a Performance & Bottleneck Analyzer for RISC-V Vector Processors
- Chuan-Hua Chang - Associate Vice President, Andes Technology
3:20pm - 3:30pm10 mins
Tech Talk
Tech Talk with Secure-IC: Overview of Secure-IC Solutions to Secure RISC-V Core
- Michel Le Rolland - Product Marketing Manager, Secure-IC
3:30pm - 3:50pm20 mins
Community Ecosystem
Does Open Hardware matter at the PCB-level?
- Jason Kridner - President of the board, BeagleBoard.org Foundation
3:50pm - 4:20pm30 mins
Meet the Speakers: Room A
LIVE Q&A Forum with Speakers: Room A
- Cesare Garlati - Founder, Hex Five Security
- Sandro Pinto - Research Scientist and Professor, Universidade do Minho
- Zdeněk Přikryl - CTO, Codasip
- Paul Shan-Chyun Ku - Deputy Technical Director of Architecture Division, Andes Technology
- Carlos Eduardo de Paula - Cloud Architect, Red Hat
- Jason Kridner - President of the board, BeagleBoard.org Foundation
- Alistair Francis - Technologist, R&D Engineering, Western Digital
- Richard Bohn - Director of RISC-V Core Development, Seagate Technology
3:50pm - 4:20pm30 mins
Meet the Speakers: Room B
LIVE Q&A Forum with Speakers: Room B
- Chuan-Hua Chang - Associate Vice President, Andes Technology
- Gernot Heiser - Professor UNSW Sydney and seL4 Evangelist, Data61, Data61 and UNSW Sydney
- Joe Circello - Technical Fellow, Chief Engineer, NXP Semiconductors, N.V.
- Mohamed Shalan - Associate Professor at the Department of Computer Science and Engineering, The American University, Cairo
- Angelos Arelakis - Chief Technology Officer, ZeroPoint Technologies AB
- Roger Espasa - CEO, SemiDynamics Technology Services
- Peter Claydon - President, Picocom
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