CALLING ALL RISC-V ADVOCATES
This year's conference program will feature exciting new projects and implementations, technical capabilities and commercial implications. Help shape the agenda by contributing your knowledge and expertise as an industry thought leader.
Deadline to Submit Your Speaking Proposal: July 10. Scroll down for submission instructions.
RISC-V Summit Track Chairs
Meet the Track Chairs for the 2020 RISC-V Summit.
Community, Ecosystem and Task Groups
The RISC-V ecosystem has shown considerable growth in the past year from the inception of the RISC-V Ambassador Program to the introduction of world-wide Virtual Meetups and continued work within the Task Groups. This track celebrates this growth by highlighting work being done to create a transparent, collaborative community devoted to building game-changing software and hardware using the RISC-V ISA.
Track Chair: Drew Fustini, Embedded Linux Engineer, BeagleBoard.org Foundation
Tell us about your test hardware, product development efforts, or newly released products. Talks covering highly detailed analysis of hardware ranging from SoCs, GPUs, to domain specific processors should focus on how RISC-V enabled product development and/or hardware ecosystem enablement.
Track Co-Chair: Allen Baum, Esperanto Tech
Track Co-Chair: Chuanhua Chang, Associate Vice President, Andes Technology
Security & Functional Safety
Integrating RISC-V with functional safety concerns (medical, industrial, automotive, or other safety-related systems) as well as talks on RISC-V innovations in a wide range of security topics like: Trusted Execution Environments, Trusted Platform Modules, homomorphic encryption, cryptographic accelerators, software/hardware attacks and countermeasures.
Track Co-Chair: Jerome Quevremont, RISC-V and Open Hardware Project Leader, Thales Research & Technology
Track Co-Chair: Helena Handschuh, Security Technologies Fellow, Rambus
Software & Tools
Verification/validation, simulation/emulation, toolchain/compiler, kernel to user space applications. Includes both commercial solutions (actively in development or deployed to customers) as well as open source projects and the ecosystems around them.
Track Chair: Arun Thomas, Distinguished Member of Technical Staff, Group Leader for Computer Systems Security, Draper Laboratories
Highlight new or novel developments in RISC-V extensions, RISC-V ISA, or RISC-V based accelerator architectures. We're looking for detailed descriptions of architectures, components, or subsystems centered around the RISC-V architecture, and efforts in building or working with these designs.
Track Co-Chair: Andy Glew, Principal Engineer/Architect, SiFive
Track Co-Chair: Kevin Chen, Senior Architect, Andes Technology
The flexibility of RISC-V offers many new challenges to the traditional SoC design verification (DV) flow as processor verification is a new requirement that almost all adopters of RISC-V will need to undertake. In line with the fresh new approaches RISC-V is enabling, this track covers the innovations in processor verification that are helping to ensure tape-out quality success across all the freedoms that RISC-V offers, with the simple goal to make the statement 'works as expected’ a reality.
Track Chair: Simon Davidmann, President & CEO, Imperas Software
How to Prepare
This year we've introduced a brand new speaker submission portal, and have included some helpful tips and key information you'll need. You will be able to edit your proposal up until the July 10th deadline.
Create your Account
Create an account to get started on your submission. You'll be able to edit your proposal up until the July 10th deadline!
You'll need speaker contact details plus their bio, including both technical expertise and past speaking experience. You may also include their LinkedIn profile / Twitter handle.
Session Title & Description
Title: Provide a session title in fewer than 10 words. Please try to include keywords and topics covered by your talk.
Description: In up to 250 words, provide a concise description of your session as you would have it appear on the RISC-V Summit website. Write in 3rd person, present tense.
Topic, format, and audience level
1) 20-minute technical session
2) 180, 90 or 60-minute deep dive technical tutorial
3) poster presentation for the Expo Floor Poster Gallery
In 3-4 bullets, tell us what the attendees will gain from this presentation and how it will benefit the RISC-V ecosystem. Give concrete examples.
It's optional to submit supplemental information that supports your session proposal. Additional materials may include white papers, demos, videos, etc.