RISC-V Summit is part of the Informa Tech Division of Informa PLC

This site is operated by a business or businesses owned by Informa PLC and all copyright resides with them. Informa PLC's registered office is 5 Howick Place, London SW1P 1WG. Registered in England and Wales. Number 3099067.


Stephen Bates
CTO at Eideticom


Stephen is a world class expert in performance storage, non-volatile memory, computer networking, signal processing and error correction coding and has worked on some of the most complicated communication and storage solutions in the industry. In his previous position, he was Senior Technical Director at Microsemi (formerly PMC) where he worked with customers, partners, internal teams and executive to shape and execute on Microsemi's roadmap for high-performance storage. Previous to Microsemi he was a cofounder and Chief Architect of Rad3 Communications, a communications IP provider which was acquired by PMC Sierra in 2011. In addition, he previously founded Raithlin Semiconductor in 2005 to deliver consulting, design services and IP solutions in the areas of Ethernet, mobile-TV, bioinformatics and home networking. Prior to Raithlin, Stephen was a professor at the University of Alberta's department of Electrical and Computer Engineering where he was affiliated with the ICORE High Capacity Digital Communications Lab. His research focused on bridging the domain between algorithm development and silicon implementation. and he was awarded both an NSERC discovery grant and a SRC research grant. Stephen holds a 1st class BEng and PhD from the University of Edinburgh.

Stephen Bates's Network

Agenda Sessions

  • Accelerating Computational Storage Over NVMe with RISC-V


Speakers at this event