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Tuesday, December 8, 2020 - PST (Pacific Standard Time, GMT-8)
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Tuesday, December 8, 2020 - PST (Pacific Standard Time, GMT-8)
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Streams
9:00am - 9:15am15 mins
Keynotes
RISC-V Unconstrained Growth and Opportunity
- Calista Redmond - CEO, RISC-V International
9:15am - 9:30am15 mins
Keynotes
RISC-V for Next Generation Storage & Compute
- Siva Sivaram - President, Technology and Strategy, Western Digital
9:30am - 9:45am15 mins
Keynotes
RISC-V Accelerating Innovation in Data Storage
- John Morris - Senior Vice President and Chief Technology Officer, Seagate Technology
9:45am - 10:00am15 mins
Keynotes
RISC-V: Good to Great
- Patrick Little - CEO, SiFive
10:00am - 10:30am30 mins
Keynotes
Building an Open Edge Machine Learning Ecosystem with RISC-V, Zephyr, TensorFlow Lite Micro and Renode
- Michael Gielda - VP Business Development, Antmicro
- Tim Ansell - Software Engineer, Google
- Brian Faith - CEO, QuickLogic Corporation
- Kate Stewart - Executive Director, Co-Founder, Zephyr Project
10:30am - 11:00am30 mins
Meet the Speakers: Room A
LIVE Q&A Forum with Keynote Speakers
11:00am - 11:20am20 mins
Community Ecosystem
Leveraging the RISC-V Eco-System to Put a Chip in Customer Hands in less than $10M
- Sean Halle - CEO, Intensivate
11:00am - 11:20am20 mins
System Architectures
A Tiny RISC-V Floating-Point Unit
- Luca Bertaccini - PhD Student, ETH Zurich
11:00am - 11:20am20 mins
Verification
Learnings from Verification of RISC-V Vector Specification
- Shubhodeep Choudhury - CEO, Valtrix Systems
- Jevin Saju John - Senior Software Engineer, Valtrix Systems
11:20am - 11:30am10 mins
Tech Talk
Tech Talk with CircuitSutra Technologies: Fast Forward your RISC-V SoC launch using SystemC based Shift-Left ESL methodologies
- Umesh Sisodia - Founder & CEO, CircuitSutra Technologies
11:30am - 11:50am20 mins
Security & Functional Safety
Tackling Safety in Space with RISC-V Based Platforms
- Jaume Abella - Senior Researcher, Barcelona Supercomputing (BSC)
11:30am - 11:50am20 mins
System Architectures
Static Partitioning Virtualization on RISC-V
- Jose Martins - PhD Student, University of Minho
- Sandro Pinto - Research Scientist and Professor, Universidade do Minho
11:30am - 11:50am20 mins
Verification
Open-source Online-TPG for RISC-V Microprocessors
- Alexander Kamkin - Leading Researcher, ISP RAS
11:50am - 12:00pm10 mins
Tech Talk
Tech Talk with Futurewei: FORCE-RISCV Instruction Stream Generator – Quick Intro
- Jingliang Wang - Principal Engineer, Futurewei Technologies
12:00pm - 12:20pm20 mins
Community Ecosystem
CANCELLED: Scale4Edge project introduction
12:00pm - 12:20pm20 mins
Hardware Cores/SoCs
NOEL-V: A new high-performance RISC-V processor family
- Alen Bardizbanyan - Hardware Engineer, Cobham Gaisler AB
- Johan Klockars - Hardware Engineer, Cobham Gaisler AB
12:00pm - 12:20pm20 mins
Security & Functional Safety
Exploring the RISC-V Vector Extension for Efficient Post-Quantum Cryptography
- Alexander Zeh - Cryptography Expert and Vice CTO, Hensoldt Cyber
12:20pm - 12:30pm10 mins
Tech Talk
Tech Talk with Antmicro: Building an open source SystemVerilog ecosystem
- Karol Gugala - Engineering Manager, Antmicro
12:30pm - 12:50pm20 mins
Community Ecosystem
Fully Open Source Manufacturable PDK for a 130nm Process
- Tim Ansell - Software Engineer, Google
12:30pm - 12:50pm20 mins
Hardware Cores/SoCs
Klessydra-T: Designing Configurable Vector Co-Processors for Multi-Threaded Edge-Computing Soft-Cores
- Mauro Olivieri - Professor, Sapienza University of Rome
12:30pm - 12:50pm20 mins
Security & Functional Safety
Standardizing the TEE with GlobalPlatform and RISC-V – The IoT Opportunity
- Gil Bernabeu - Technical Director, GlobalPlatform
12:50pm - 1:30pm40 mins
Meet the Speakers: Room A
LIVE Q&A Forum with Speakers: Room A
- Shubhodeep Choudhury - CEO, Valtrix Systems
- Jevin Saju John - Senior Software Engineer, Valtrix Systems
- Alexander Kamkin - Leading Researcher, ISP RAS
- Alen Bardizbanyan - Hardware Engineer, Cobham Gaisler AB
- Johan Klockars - Hardware Engineer, Cobham Gaisler AB
- Mauro Olivieri - Professor, Sapienza University of Rome
- Luca Bertaccini - PhD Student, ETH Zurich
12:50pm - 1:30pm40 mins
Meet the Speakers: Room B
LIVE Q&A Forum with Speakers: Room B
- Alexander Zeh - Cryptography Expert and Vice CTO, Hensoldt Cyber
- Gil Bernabeu - Technical Director, GlobalPlatform
- Sean Halle - CEO, Intensivate
- Jaume Abella - Senior Researcher, Barcelona Supercomputing (BSC)
- Tim Ansell - Software Engineer, Google
- Sandro Pinto - Research Scientist and Professor, Universidade do Minho
- Jose Martins - PhD Student, University of Minho
1:30pm - 1:50pm20 mins
Software & Tools
RISC-V Software State of the Union
- Arun Thomas - Distinguished Scientist, Draper Laboratory
1:30pm - 1:50pm20 mins
System Architectures
RISC-V Vector Extensions for Scaling Intelligence to the Edge
- Krste Asanovic - Professor | Chief Architect, UC Berkeley | SiFive
1:30pm - 1:50pm20 mins
Verification
Comprehensive Pre-Si Verification of RISC-V Cores in a Storage Controller
- Bill McSpadden - Principal Verification Engineer, Seagate Technology
1:50pm - 2:00pm10 mins
Tech Talk
Tech Talk with OpenHW Group: CORE-V Verification Test Bench
- Mike Thompson - Director of Verification Engineering, OpenHW Group
2:00pm - 2:20pm20 mins
Community Ecosystem
Linux on Open Hardware with RISC-V
- Drew Fustini - Embedded Linux Engineer, BeagleBoard.org Foundation
2:00pm - 2:20pm20 mins
Software & Tools
An Open-Source Flow for DNNs on Ultra-Low-Power RISC-V Cores
- Francesco Conti - Assistant Professor, University of Bologna
2:00pm - 2:20pm20 mins
Software and Tools 2
Debug and Trace of Complex Heterogeneous SOC
- Dennis Griffith - Field Application Engineer, Lauterbach
2:20pm - 2:30pm10 mins
Tech Talk
Tech Talk with SiFive: SiFive RISC-V Core IP Products
- Drew Barbier - Director, Product Marketing, Core IP, SiFive
2:30pm - 2:50pm20 mins
Hardware Cores/SoCs
Esperanto Accelerates Machine Learning With RISC-V
- Art Swift - CEO, Esperanto Technologies
2:30pm - 2:50pm20 mins
Security & Functional Safety
Data Trustworthiness at the Edge
- Manuel Offenberg - Technologist, Seagate
2:30pm - 2:50pm20 mins
Software & Tools
OpenJ9 JDK on RISC-V
- Cheng Jin - OpenJ9 VM Software Developer, IBM
2:50pm - 3:00pm10 mins
Tech Talk
Tech Talk with Segger: In a nutshell: Debugging RISC-V based Embedded Systems
- Axel Wolf - Sr. Staff FAE, Segger Microcontroller Systems
3:00pm - 3:20pm20 mins
Hardware Cores/SoCs
Andes RISC-V Processor IP Solutions
- Charlie Su - CTO and SVP of R&D, Andes Technology Corporation
3:00pm - 3:20pm20 mins
Security & Functional Safety
Spectre on Hybrid multi-core RISC-V
- Anh Tien Le - PhD Student, VLSILAB UEC
3:00pm - 3:20pm20 mins
Software & Tools
rvnewop: A RISCV New Instruction Recommender System
- Nagendra Gulur - Assistant Professor, University of North Texas
3:20pm - 3:30pm10 mins
Tech Talk
Tech Talk with Andes: OpenCL for RISC-V
- Shao-Chung Wang - Deputy Manager of Software Division, Andes Technology
3:30pm - 3:50pm20 mins
Hardware Cores/SoCs
CORE-V MCU SoC, Open Source, 22nm Embedded MCU with eFPGA
- Florian Zaruba - Director of Engineering, HW & SW Task Groups, OpenHW Group
3:30pm - 3:50pm20 mins
Software & Tools
kexec based bootloaders on RISC-V: Use-cases and Advantages
- Bhupesh Sharma - Senior Software Engg, Red Hat
3:30pm - 3:50pm20 mins
System Architectures
Building Cache-coherent Scaleout Systems with Omnixtend
- Atish Patra - Technologist, Western Digital
- Tu Dang - Technologist, Western Digital
3:30pm - 3:50pm20 mins
Verification
Getting started with RISC-V Processor Verification
- Lee Moore - Lead Engineer, Imperas
3:50pm - 4:00pm10 mins
Tech Talk
Tech Talk with Lampro Mellon: An Open-Source Solution for Accelerating Verification of RISC-V Processors
- Bilal Zafar - VP Engineering, Lampro Mellon
- Haroon Shafique - Associate Design Engineer, Lampro Mellon
4:00pm - 4:30pm30 mins
Meet the Speakers: Room A
LIVE Q&A Forum with Speakers: Room A
- Krste Asanovic - Professor | Chief Architect, UC Berkeley | SiFive
- Drew Fustini - Embedded Linux Engineer, BeagleBoard.org Foundation
- Arun Thomas - Distinguished Scientist, Draper Laboratory
- Francesco Conti - Assistant Professor, University of Bologna
- Cheng Jin - OpenJ9 VM Software Developer, IBM
- Nagendra Gulur - Assistant Professor, University of North Texas
- Bhupesh Sharma - Senior Software Engg, Red Hat
- Anh Tien Le - PhD Student, VLSILAB UEC
4:00pm - 4:30pm30 mins
Meet the Speakers: Room B
LIVE Q&A Forum with Speakers: Room B
- Bill McSpadden - Principal Verification Engineer, Seagate Technology
- Dennis Griffith - Field Application Engineer, Lauterbach
- Art Swift - CEO, Esperanto Technologies
- Charlie Su - CTO and SVP of R&D, Andes Technology Corporation
- Florian Zaruba - Director of Engineering, HW & SW Task Groups, OpenHW Group
- Manuel Offenberg - Technologist, Seagate
- Atish Patra - Technologist, Western Digital
- Tu Dang - Technologist, Western Digital
- Lee Moore - Lead Engineer, Imperas
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