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Tuesday, December 8, 2020keyboard_arrow_right

Tuesday, December 8, 2020 - PST (Pacific Standard Time, GMT-8)

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Tuesday, December 8, 2020 - PST (Pacific Standard Time, GMT-8)

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9:00am - 9:15am15 mins
Keynotes
RISC-V Unconstrained Growth and Opportunity
  • Calista Redmond - CEO, RISC-V International
9:15am - 10:00am45 mins
Keynotes
Keynote Program
    10:00am - 10:30am30 mins
    Keynotes
    Building an Open Edge Machine Learning Ecosystem with RISC-V, Zephyr, TensorFlow Lite Micro and Renode
    • Michael Gielda - VP Business Development, Antmicro
    • Tim Ansell - Software Engineer, Google
    • Brian Faith - CEO, QuickLogic Corporation
    • Kate Stewart - Executive Director, Co-Founder, Zephyr Project
    10:30am - 11:00am30 mins
    Meet the Speakers
    LIVE Q&A Forum with Keynote Speakers
      11:00am - 11:20am20 mins
      Community Ecosystem
      Leveraging the RISC-V Eco-System to Put a Chip in Customer Hands in less than $10M
      • Sean Halle - CEO, Intensivate
      11:00am - 11:20am20 mins
      System Architectures
      A Tiny RISC-V Floating-Point Unit
      • Luca Bertaccini - PhD Student, ETH Zurich
      11:00am - 11:20am20 mins
      Verification
      Learnings from Verification of RISC-V Vector Specification
      • Shubhodeep Choudhury - CEO, Valtrix Systems
      • Jevin Saju John - Senior Software Engineer, Valtrix Systems
      11:30am - 11:50am20 mins
      Security & Functional Safety
      Tackling Safety in Space with RISC-V Based Platforms
      • Paco Gomez Molinero - Director, Fent Innovative Software Solutions - fentISS
      11:30am - 11:50am20 mins
      System Architectures
      Static Partitioning Virtualization on RISC-V
      • Jos Martins - PhD Student, University of Minho
      • Sandro Pinto - Research Scientist and Professor, Universidade do Minho
      11:30am - 11:50am20 mins
      Verification
      Open-source Online-TPG for RISC-V Microprocessors
      • Alexander Kamkin - Leading Researcher, ISP RAS
      12:00pm - 12:20pm20 mins
      Community Ecosystem
      Scale4Edge project introduction
      • Wolfgang Ecker - Lead Principle Engineer, Infineon Technologies
      12:00pm - 12:20pm20 mins
      Hardware Cores/SoCs
      NOEL-V: A new high-performance RISC-V processor family
      • Alen Bardizbanyan - Hardware Engineer, Cobham Gaisler AB
      • Johan Klockars - Hardware Engineer, Cobham Gaisler AB
      12:00pm - 12:20pm20 mins
      Security & Functional Safety
      Exploring the RISC-V Vector Extension for Efficient Post-Quantum Cryptography
      • Alexander Zeh - Cryptography Expert and Vice CTO, Hensoldt Cyber
      12:30pm - 12:50pm20 mins
      Community Ecosystem
      Fully Open Source Manufacturable PDK for a 130nm Process
      • Tim Ansell - Software Engineer, Google
      12:30pm - 12:50pm20 mins
      Hardware Cores/SoCs
      Klessydra-T: Designing Configurable Vector Co-Processors for Multi-Threaded Edge-Computing Soft-Cores
      • Mauro Olivieri - Professor, Sapienza University of Rome
      12:30pm - 12:50pm20 mins
      Security & Functional Safety
      Standardizing the TEE with GlobalPlatform and RISC-V – The IoT Opportunity
      • Gil Bernabeu - Technical Director, GlobalPlatform
      12:50pm - 1:30pm40 mins
      Meet the Speakers
      LIVE Q&A Forum with Speakers
        1:30pm - 1:50pm20 mins
        Community Ecosystem
        Linux on Open Hardware with RISC-V
        • Drew Fustini - Embedded Linux Engineer, BeagleBoard.org Foundation
        1:30pm - 1:50pm20 mins
        Software & Tools
        RISC-V Software State of the Union
        • Arun Thomas - Distinguished Scientist, Draper Laboratory
        1:30pm - 1:50pm20 mins
        Verification
        Comprehensive Pre-Si Verification of RISC-V Cores in a Storage Controller
        • Bill McSpadden - Principal Verification Engineer, Seagate Technology
        2:00pm - 2:20pm20 mins
        Software & Tools
        An Open-Source Flow for DNNs on Ultra-Low-Power RISC-V Cores
        • Francesco Conti - Assistant Professor, University of Bologna
        2:00pm - 2:20pm20 mins
        System Architectures
        RISC-V Vector Extensions for Scaling Intelligence to the Edge
        • Krste Asanovic - Professor | Chief Architect, UC Berkeley | SiFive
        2:30pm - 2:50pm20 mins
        Hardware Cores/SoCs
        Esperanto Accelerates Machine Learning With RISC-V
        • Art Swift - CEO, Esperanto Technologies
        2:30pm - 2:50pm20 mins
        Security & Functional Safety
        Data Trustworthiness at the Edge
        • Manuel Offenberg - Technologist, Seagate
        2:30pm - 2:50pm20 mins
        Software & Tools
        OpenJ9 JDK on RISC-V
        • Cheng Jin - OpenJ9 VM Software Developer, IBM
        3:00pm - 3:20pm20 mins
        Hardware Cores/SoCs
        Andes RISC-V Processor IP Solutions
        • Charlie Su - CTO and SVP of R&D, Andes Technology Corporation
        3:00pm - 3:20pm20 mins
        Security & Functional Safety
        Spectre on Hybrid multi-core RISC-V
        • Anh Tien Le - PhD Student, VLSILAB UEC
        3:00pm - 3:20pm20 mins
        Software & Tools
        rvnewop: A RISCV New Instruction Recommender System
        • Nagendra Gulur - Assistant Professor, University of North Texas
        3:30pm - 3:50pm20 mins
        Hardware Cores/SoCs
        Xuantie 910, A Silicon-Proven High-Performance AI Accelerated Processor
        • Chang Liu - Senior Engineer, Alibaba
        3:30pm - 3:50pm20 mins
        Software & Tools
        kexec based bootloaders on RISC-V: Use-cases and Advantages
        • Bhupesh Sharma - Senior Software Engg, Red Hat
        3:30pm - 3:50pm20 mins
        System Architectures
        Wujian：An Open-source FPGA-based SoC Platform Brings RISC-V Innovation to Alibaba Cloud
        • Kuan Zhao, T-Head Semiconductor Co. Ltd.
        3:50pm - 4:20pm30 mins
        Meet the Speakers
        LIVE Q&A Forum with Speakers or Happy Hour
          NextWednesday, December 9, 2020
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