RISC-V Summit is part of the Informa Tech Division of Informa PLC

This site is operated by a business or businesses owned by Informa PLC and all copyright resides with them. Informa PLC's registered office is 5 Howick Place, London SW1P 1WG. Registered in England and Wales. Number 3099067.

Informa
Key Sessions
Calista Redmond
Welcome Address: Exponential Progress across Industries and Around the World with RISC-V
RISC-V Foundation
Krste Asanovic
State of the Union
UC Berkeley | SiFive
Martin Fink
Unshackling Memory!
Western Digital
Junho Huh
RISC-V of Samsung in the Age of 5G and AI
Samsung Electronics
keyboard_arrow_right

Tuesday, December 10

keyboard_arrow_leftSearch & Filter
search

Tuesday, December 10

search
8:00am - 7:00pm660 mins
Registration
Registration
    9:00am - 9:20am20 mins
    Keynotes
    Welcome Address: Exponential Progress across Industries and Around the World with RISC-V
    • Calista Redmond - CEO, RISC-V Foundation
    9:20am - 10:00am40 mins
    Keynotes
    State of the Union
    • Krste Asanovic - Professor | Chief Architect, UC Berkeley | SiFive
    10:00am - 10:20am20 mins
    Keynotes
    Unshackling Memory!
    • Martin Fink, Western Digital
    10:20am - 10:40am20 mins
    Keynotes
    Open for Business: True Stories of How Far We’ve Come With the RISC-V Ecosystem
    • Ted Speers - Head of Product Planning for FPGA Business, Microchip Technology Inc.
    10:40am - 10:50am10 mins
    Keynotes
    Lightning Talks featuring Chronos Tech, Solid Sands and Think Silicon
    • Marianne Damstra - CCO, Solid Sands
    • Stefano Giaconi - Cofounder & CTO, Chronos Tech
    • Ulli Mueller - Senior Vice President Sales & Marketing, Think Silicon, Think Silicon
    10:50am - 11:10am20 mins
    Keynotes
    RISC-V of Samsung in the Age of 5G and AI
    • Junho Huh - VP, Next Generation Architecture, Samsung Electronics, Samsung Electronics
    11:10am - 11:30am20 mins
    Keynotes
    Ruby Sponsor SiFive presents: Taking RISC-V into New Markets
    • Yunsup Lee - CTO, SiFive
    11:30am - 7:00pm450 mins
    Expo
    Expo Hall
      11:30am - 12:50pm80 mins
      Networking
      Lunch Break
        11:30am - 7:00pm450 mins
        Poster Gallery
        Poster Gallery on Expo Floor
        • Chuan-Hua Chang - Managing Director, Andes Technology Corporation
        • Huynh Tu Dang - Principal Engineer, Western Digital Corperation
        • Alexander Kamkin - Leading Researcher, ISP RAS
        • Nick Kossifidis - Principal Research Engineer, ICS-FORTH
        • Paul Loewenstein - Senior Technologist, Western Digital
        • Allen Lu - AI compiler manager, Peakhills Group Corporation
        • Arjun Menon - Senior Project Officer, IIT Madras | Shakti Project
        • Sandro Pinto - Research Scientist and Invited Professor, Universidade do Minho
        • Jim Straus - Senior Consulting Engineer, Imperas Software
        • Greg Sullivan - Chief Scientist, Dover Microsystems
        • Weifeng Zhang - Chief Scientist of Heterogeneous Computing, Alibaba Group
        12:50pm - 1:10pm20 mins
        Hardware/Architecture
        Code Size of RISC-V versus ARM using the Embench™ 0.5 Benchmark Suite: What is the Cost of ISA Simplicity?
        • David Patterson - Vice Chair, RISC-V Foundation
        12:50pm - 1:10pm20 mins
        Security/Verification
        Emerald Sponsor Microchip presents: Getting started with PolarFire SoC
        • Hugh Breslin - Design Engineer, Microchip Technology
        • Anton Krug - Development Engineer, Microchip Technology
        12:50pm - 1:10pm20 mins
        Software
        Linux on RISC-V -- Fedora and Firmware Status Update
        • Wei Fu - Software Engineer, Red Hat
        1:20pm - 1:40pm20 mins
        Hardware/Architecture
        Every CPU Cycle Counts
        • Gajinder Panesar - CTO, UltraSoC
        • Iain Robertson - VP Engineering, UltraSoC
        1:20pm - 1:40pm20 mins
        Security/Verification
        Architectural Extensions for a RISC-V Processor for Embedded Security
        • Tariq Kurd - CPU Architect, Huawei UK
        1:20pm - 1:40pm20 mins
        Software
        Headline Sponsor Western Digital presents: GCC Compiler: Code Size Density
        • Nidal Faour - Staff Engineer, R&D Engineering - Firmware & Toolchain, CTO Group, Western Digital
        • Ofer Shinaar - Manager, R&D Engineering – Firmware & Toolchain, CTO Group, Western Digital
        1:50pm - 2:00pm10 mins
        Hardware/Architecture
        A RISC-V ISA Extension for Ultra-Low Power IoT Wireless Signal Processing
        • Zdenek Prikryl - CTO, Codasip
        1:50pm - 2:10pm20 mins
        Security/Verification
        System-Level Security Verification of RISC-V Based SoCs
        • Nicole Fern - Senior Hardware Security Engineer, Tortuga Logic, Inc.
        1:50pm - 2:10pm20 mins
        Software
        Open Source Compiler Tool Chains for RISC-V: Past, Present and Future
        • Jeremy Bennett - Chief Executive, Embecosm
        2:00pm - 2:10pm10 mins
        Hardware/Architecture
        Software PPA Metrics: Results from Real-world MCU Security Applications
        • Joe Circello - Fellow, Chief MCU Core Platform & Security Architect, NXP Semiconductors, N.V.
        2:20pm - 2:40pm20 mins
        Hardware/Architecture
        An Open and Coherent Memory Centric Architecture Enabled by RISC-V
        • Dejan Vucinic - Director, NVM Systems Architecture, Western Digital
        2:20pm - 3:10pm50 mins
        Security/Verification
        The RISC-V Open ISA’s shock Wave of Processor Innovation that's Causing a Seismic Shift in SoC Verification Requirements
        • Ann Mutschler - Executive Editor/EDA, Semiconductor Engineering
        • Simon Davidmann - CEO, Imperas
        • Richard Ho - Principal Hardware Engineer, Google
        • Emerson Hsiao - Senior VP, Andes Technology USA Corp.
        • Dave Kelf - Chief Marketing Officer, Breker Verification Systems
        • Frank Schirrmeister - Senior Group Director, Product Management, System Development, System & Verification Group (SVG), Cadence Design Systems, Inc.
        • Mike Thompson - Director of Verification Engineering, OpenHW Group
        2:20pm - 2:40pm20 mins
        Hardware/Architecture.
        Ruby Sponsor SiFive presents: The Open Secure Platform Architecture of SiFive Shield
        • Dany Nativel - Security Director, SiFive
        2:50pm - 3:10pm20 mins
        Hardware/Architecture
        Software Flow for Complex SoC-FPGA
        • Cyril Jean - Director, Embedded Systems Solutions, Microchip Technology
        2:50pm - 3:10pm20 mins
        Software
        The RISC-V Journey Through Containers to the Cloud
        • Carlos Eduardo de Paula - Senior Cloud Architect, Red Hat
        3:10pm - 3:40pm30 mins
        Networking
        Networking Break
          3:40pm - 3:50pm10 mins
          Hardware/Architecture
          Avoiding Amdahl's Law: RISC-V Architecture Exploration for AI & ML Many-core Compute Arrays
          • Simon Davidmann - CEO, Imperas
          3:40pm - 4:00pm20 mins
          Security/Verification
          Introducing Scalable New Core IP for Mission Critical Use
          • Aniket Saha - Director of Product Marketing, SiFive
          • Murali Vijayaraghavan - Principal Engineer, SiFive
          3:40pm - 4:00pm20 mins
          Software
          Developing with FreeRTOS and RISC-V
          • Richard Barry - Founder | Principal Engineer, FreeRTOS | Amazon Web Services
          3:50pm - 4:00pm10 mins
          Hardware/Architecture
          Scalable, Configurable Neural Network Accelerator Based on RISC-V Core
          • Karthik Wali - Staff Digital Design Engineer, LG Electronics
          4:10pm - 4:30pm20 mins
          Hardware/Architecture
          Enabling the Full Power of a Multiprocessor SoC
          • Jeff Hancock - Senior Product Manager, Mentor (a Siemens Company)
          4:10pm - 4:30pm20 mins
          Security/Verification
          Open Source Verification Platform for RISC-V Processors
          • Tao Liu - Senior Hardware Engineer, Google
          • Richard Ho - Principal Hardware Engineer, Google
          4:10pm - 4:30pm20 mins
          Software
          Next-generation IDE for your RISC-V Product in 20 Minutes
          • Ivan Kravets - CEO, PlatformIO
          4:40pm - 5:00pm20 mins
          Hardware/Architecture
          RISC-V in Practical Education of Computer Architecture
          • Stefan Wallentowitz - Professor, Munich University of Applied Sciences
          4:40pm - 5:00pm20 mins
          Security/Verification
          Democratising Formal Verification of RISC-V Processors
          • Ashish Darbari - CEO, Axiomise Limited
          4:40pm - 5:00pm20 mins
          Software
          SEGGER presents: Visualizing and Recording the true Runtime Behavior of a RISC-V based Application -- in real-time
          • Axel Wolf - Sr. Staff Field Applications Engineer, SEGGER Microcontroller LLC
          5:10pm - 5:30pm20 mins
          Hardware/Architecture
          The Next Generation of GAP8: An IoT Application Processor for Inference at the Very Edge
          • Martin Croome - VP, Business Development, Greenwaves Technologies
          5:10pm - 5:30pm20 mins
          Security/Verification
          RISC-V and a Meta-framework Security Certification Approach for a Secure Connected World
          • John Boggie - Director, Head of Cybersecurity Certification, NXP Semiconductors
          5:10pm - 5:30pm20 mins
          Software
          Code Density Improvements Beyond The C Standard Extension
          • Zdenek Prikryl - CTO, Codasip
          5:30pm - 7:00pm90 mins
          Networking
          Welcome Happy Hour
            NextWednesday, December 11
            Filter
            Streams
            Topics
            Choose Day