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9:00am - 10:00am 60 mins
Registration: Open 9AM - 6PM
10:30am - 12:00pm 90 mins
Info
Tutorial: Running the Zephyr RTOS and Machine Learning with TensorFlow Lite on RISC-V
  • Pete Warden - Staff Research Engineer, Google
  • Peter Zierhoffer - Team Leader -- Renode, Antmicro

Edge AI capabilities of modern systems enable machine learning tasks to be performed closer to where the data is being produced, eliminating the need for power-inefficient communication with the cloud, minimizing privacy concerns and reducing latency. Originally targeting smartphones, Google's TensorFlow Lite framework now ventures to support even very small devices in performing ML tasks in a unified and user-friendly way, and has recently added RISC-V support. The Zephyr RTOS on the other hand enables a Linux-like programming experience for small embedded devices, providing a unified OS platform for use cases where Linux is simply too big.

In this tutorial, we will show how RISC-V can be used on edge devices to run a standard RTOS and perform machine learning tasks on RISC-V hardware. You will learn about current status of Zephyr and TF Lite and plans for TF Lite RISC-V support, developing with Zephyr and TF Lite on real hardware, testing with the open source Renode framework, and more.

Location: 2nd Floor Meeting Rooms 209/210

12:00pm - 1:30pm 90 mins
Lunch
12:00pm - 1:30pm 90 mins
Lunch
1:30pm - 3:00pm 90 mins
Info
Formal Verification of RISC-V processor implementations -- Space Limited!
  • Edmund Humbenberger - CEO, Symbiotic
  • Clifford Wolf - CTO, Symbiotic EDA

Location: 2nd Floor Meeting Rooms 209/210

Learn how to use formal Assertion Based Verification (ABV) and open-source tools to formally verify HDL designs, and how to use the properties and formal test benches in the riscv-formal framework to formally verify RISC-V cores with ease.

This tutorial is aimed specifically at HDL design engineers without in-depth knowledge of formal methods who want to add formal ABV to their verification toolbox.

1:30pm - 3:00pm 90 mins
Info
Running a Linux-Capable Open Source Soft SoC on the Avalanche Board with MicroSemi PolarFire FPGA
  • Karol Gugala - Team Lead, Antmicro
  • Bill Pratt - Regional Technical Director, Future Electronics

Location: 2nd Floor Meeting Rooms 203/204

As an open and flexible standard, the RISC-V ISA is an excellent match for both ASIC and FPGA implementations. The availability of open source cores with mainstream tooling is breathing new life into the open hardware and IP space, making it feasible for the first time to create open source SoCs which can be made available to everyone at no cost other than a simple board. With open tooling support and a connection to the broader RISC-V ecosystem, the open source soft FPGA SoC based on LiteX/VexRiscV can serve as an entry point to open source digital design. The open source SoC running Linux on the new MicroSemi PolarFire FPGA will be presented and explained, and the capabilities offered by a flexible, Linux-enabled FPGA RISC-V platform will be discussed and explored in this tutorial by Antmicro and Microchip.

3:00pm - 3:30pm 30 mins
Networking Break
3:00pm - 3:30pm 30 mins
Networking Break
3:30pm - 5:00pm 90 mins
Info
Tutorial: Easy-to-use, FPGA-Accelerated Hardware Simulation of RISC-V Hardware Designs with FireSim on Amazon EC2 F1
  • Alon Amid - Graduate Student, UC Berkeley
  • Sagar Karandikar - Graduate Student, UC Berkeley
  • David Biancolin - Graduate Student, UC Berkeley

Location: 2nd Floor Meeting Rooms 203/204

We present a tutorial for FireSim (https://fires.im), an easy-to-use, open-source, FPGA-accelerated cycle-accurate hardware simulation platform developed at UC Berkeley that runs on Amazon EC2 F1. FireSim automatically transforms and instruments open-hardware designs (e.g. RISC-V Rocket Chip and BOOM) using the MIDAS framework into fast, deterministic, FPGA-based simulators that enable productive pre-silicon verification and performance validation. By providing a framework to automate the management of FPGA infrastructure, FireSim also lets software developers get a head-start on building software for a novel hardware design, by letting these developers interact with the pre-silicon hardware design as they would a virtual machine. In effect, both hardware and software developers work from a single source of truth: the RTL for the hardware design. Leveraging AWS EC2 F1, FireSim removes the high capex and management complexity traditionally involved in large-scale FPGA-based simulation, democratizing access to realistic pre-silicon hardware modeling of new designs. In this half-day tutorial, we cover the open-source FireSim framework, explore how users can use and modify the existing designs available in FireSim, and show how users can integrate and measure their own hardware designs.

5:00pm - 7:00pm 120 mins
Info
RISC-V Summit Welcome Happy Hour -- Sponsored by Ashling

Join us at the "Welcome to the RISC-V Summit" Happy Hour, celebrating the first RISC-V Summit! Doors open on Dec. 3rd at 5pm. Don't miss your chance to network over drinks with your peers, colleagues and industry luminaries. 

Location: 2nd Floor Meeting Rooms 209/210

9:00am - 10:00am

Registration: Open 9AM - 6PM

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Showing of Streams
5:00pm - 7:00pm
Info

RISC-V Summit Welcome Happy Hour -- Sponsored by Ashling

Join us at the "Welcome to the RISC-V Summit" Happy Hour, celebrating the first RISC-V Summit! Doors open on Dec. 3rd at 5pm. Don't miss your chance to network over drinks with your peers, colleagues and industry luminaries. 

Location: 2nd Floor Meeting Rooms 209/210

More