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Key Sessions

David Patterson

A New Golden Age for Computer Architecture: History, Challenges, and Opportunities

RISC-V Foundation

Yunsup Lee

Opportunities and Challenges of Building Silicon in the Cloud

SiFive

Rob Oshana

Deepening the RISC-V Ecosystem to Drive Industry-Wide Adoption

NXP

Michael Gielda

Accelerating Innovation: Why Google's TPU Was Just the Start

Antmicro

Greg Wright

RISC-V: Opportunities and challenges in SoCs

Qualcomm Technologies, Inc.

8:00am - 8:25am 25 mins
Keynotes
Registration Open: 8:00 AM - 5:30 PM
8:25am - 8:30am 5 mins
Keynotes
Welcome
8:30am - 9:00am 30 mins
Info
Keynotes
A New Golden Age for Computer Architecture: History, Challenges, and Opportunities
  • David Patterson - Vice Chair, RISC-V Foundation

Location: 1st Floor, Exhibit Hall A-1

In the 1980s, Mead and Conway democratized chip design and high-level language programming surpassed assembly language programming, which made instruction set advances viable. Innovations like Reduced Instruction Set Computers (RISC), superscalar, and speculation ushered in a Golden Age of computer architecture, when performance doubled every 18 months. The ending of Dennard Scaling and Moore’s Law crippled this path; microprocessor performance improved only 3% last year!

The ending of Dennard scaling and Moore’s law and the deceleration of performance gains for standard microprocessors are not problems that must be solved but facts that if accepted offer breathtaking opportunities. We believe high-level, domain-specific languages and architectures and freeing architects from the chains of proprietary instruction sets will usher in a new Golden Age. Aided by open source ecosystems, agilely developed chips will convincingly demonstrate advances and thereby accelerate commercial adoption. The instruction set philosophy of the general-purpose processors in these chips will likely be RISC, which has stood the test of time. We envision the same rapid improvement as in the last Golden Age, but this time in cost and energy as well as in performance.

Like the 1980s, the next decade will be exciting for computer architects in academia and in industry!


9:00am - 9:20am 20 mins
Info
Keynotes
Opportunities and Challenges of Building Silicon in the Cloud
  • Yunsup Lee - CTO, SiFive

Location: 1st Floor, Exhibit Hall A-1

9:20am - 9:40am 20 mins
Info
Keynotes
Deepening the RISC-V Ecosystem to Drive Industry-Wide Adoption
  • Rob Oshana - Co-Chair, Program Committee | VP Software Engineering, NXP

Location: 1st Floor, Exhibit Hall A-1

9:40am - 10:00am 20 mins
Info
Keynotes
Accelerating Innovation: Why Google's TPU Was Just the Start
  • Michael Gielda - VP Business Development, Antmicro

Location: 1st Floor, Exhibit Hall A-1

10:00am - 10:40am 40 mins
Keynotes
Networking Break on the Expo Floor
10:00am - 10:15am 15 mins
Info
Expo
Exhibit Hall Open: 10AM - 3:30PM

Location: 1st Floor, Exhibit Hall A-2 & A-3

10:15am - 12:35pm 140 mins
Info
Expo
RISC-V Linux Hackathon: 10AM - 3:00PM

Don't miss out on the RISC-V Linux Hackathon, happening Dec. 4-5 on the Expo Floor at the RISC-V Summit.

Watch as a team of 10 expert hackers create cutting edge applications on a soft RISC-V CPU running Linux on the low-cost Avalanche FPGA board. Thanks to Western Digital for organizing!

10:40am - 11:20am 40 mins
Info
Keynotes
Keynote Panel: Opportunities and Challenges in Security for Open Source Hardware
  • Moderator Ed Sperling - Editor In Chief, Semiconductor Engineering
  • Panelist Helena Handschuh - Chair of the RISC-V Foundation Security Standing Committee | Fellow, Rambus
  • Panelist Joseph Kiniry - Principal Scientist, Galois
  • Panelist Richard Newell - Senior Principal Product Architect, Microsemi, a Microchip Company

Location: 1st Floor, Exhibit Hall A-1

Since the publication of the devastating Spectre and Meltdown attacks on Intel and ARM processors earlier this year, closely followed by Ryzenfall on AMD processors, the computer architecture community has woken up to the very real threats this new generation of side-channel attacks represent for proprietary processor designs and instruction set architectures. On the other end of the spectrum, the open source hardware community has been working on bringing the RISC-V instruction set architecture into the public domain and created its own foundation to move open source hardware principles forward. That community too has recently woken up to the urgency of addressing security issues and to the question of how to build secure processors based on its open instruction set. This panel of recognized security experts will discuss: 

  • some of the newly emerging threats on processors such as the newest TLBleed, speculative buffer overflow and timing side-channel attacks which yet again show how vulnerable processors are to side-channel attacks. 
  • some of the advantages of the RISC-V approach to counter these types of threats, 
  • which particular threats may still be a concern even for RISC-V processors beyond the traditional proprietary processor architectures. 
  • work that has been undertaken by the RISC-V Foundation to add security features and relevant extensions to the RISC-V instruction set architecture to start aligning RISC-V processing with the required security extensions, basic building blocks and primitives required for secure execution.
11:20am - 11:40am 20 mins
Info
Keynotes
RISC-V: Opportunities and challenges in SoCs
  • Greg Wright - Sr. Director, Engineering, Qualcomm Technologies, Inc.

Location: 1st Floor, Exhibit Hall A-1

11:40am - 1:10pm 90 mins
Keynotes
Lunch
1:10pm - 1:30pm 20 mins
Info
Open RISC-V Platforms
Running Other Architecture Operating Systems and Applications on RISC-V Using QEMU
  • Alistair Francis - Principal Engineer, Western Digital

Location: 2nd Floor Meeting Room 203/204

QEMU allows running an operating system compiled for a different architecture on the current architecture. This is commonly used to develop and debug embedded systems (such as ARM architectures) on Intel workstations (x86). Currently mainline QEMU supports RISC-V guests, allowing development and debugging of RISC-V operating systems on Intel machines. This presentation focuses on allowing x86 operating systems to run on the RISC-V architecture using QEMU. It also discusses the work involved in upstreaming the implementation. Using this we can run the first instance of QEMU to emulate a RISC-V machine on an x86 workstation. We can then start a second QEMU instance inside the first one to run x86 operating systems on top of the RISC-V machine. The same setup can be used on a real RISC-V board.

1:10pm - 1:30pm 20 mins
Info
RISC-V Accelerators
Domain-Specific Acceleration via AndeStar V5 Processors
  • Charlie Su - CTO and SVP of R&D, Andes Technology Corporation

Location: 1st Floor, Exhibit Hall A-1

Application-Specific Instruction Processors (ASIP's) or Purpose-Built Accelerators have been popular for years in applications where performance is demanding, and cost and power are sensitive. As Moore's Law approaches the end of its life, DSA (Domain-Specific Architecture) becomes even more important to continue to carry the ever-increasing computing demands forward. 

In this talk, we will:

  • Give an update of Andes V5 processor solutions. 
  • Introduce a comprehensive solution to unlock the potential DSA in RISC-V.
  • Explain how a powerful tool COPILOT greatly simplifies design and verification of advanced custom instructions. 
  • Use practical examples to demonstrate how our solutions help solving real-world problems.
1:10pm - 1:30pm 20 mins
Info
Secure RISC-V
If We Get RISC-V Security Right, It Will Become the Dominant Processor in the $470B IoT Market
  • Jothy Rosenberg - CEO & Founder, Dover Microsystems

Location: 2nd Floor Meeting Room 209/210

The IoT "cyber epidemic" is an existential threat to civilized society. We are dangerously vulnerable to this threat because bugs in software let attackers in, and defenseless processors do their bidding. This must be addressed in hardware at the processor level. With its low barriers to entry and no legacy requirements to support, we have a unique opportunity with RISC-V to truly fix this problem. We can protect a RISC-V core from network-based attacks --without changing it -- using three key innovations. 

  1. First, generate metadata about the intent of the application to provide a co-processor with information unavailable in today's standard development environments. 
  2. Second, apply a set of rules called micro-policies to describe the security properties we want to maintain and enforce. 
  3. And third, create simple but powerful hardware mechanism that watches every instruction, examines the critical metadata, and evaluates the aforementioned rules to block any instruction doing the wrong thing. 

The RISC-V community is ideally suited to wield this revolutionary technology to create processors that can dominate the burgeoning IoT market, while making our connected world a safer and more secure place.

1:10pm - 1:30pm 20 mins
Info
Expo
Exhibit Hall Open: 10AM - 3:30PM

Location: 1st Floor, Exhibit Hall A-2 & A-3

1:30pm - 3:00pm 90 mins
Info
Expo
RISC-V Linux Hacakthon: 10AM - 3:00PM

Don't miss out on the RISC-V Linux Hackathon, happening Dec. 4-5 on the Expo Floor at the RISC-V Summit.

Watch as a team of 10 expert hackers create cutting edge applications on a soft RISC-V CPU running Linux on the low-cost Avalanche FPGA board. Thanks to Western Digital for organizing!

1:40pm - 2:00pm 20 mins
Info
Open RISC-V Platforms
How to Address RISC-V Compliance in the Era of OPEN ISA and Custom Instructions
  • Simon Davidmann - CEO, Imperas
  • Lee Moore - Lead Engineer, Imperas

Location: 2nd Floor Meeting Room 203/204

One mission-critical task for the RISC-V SoC developers and implementors is the need to test and verify that RISC-V cores are compliant to the specifications, including user and privilege modes. The RISC-V market will depend on the wide and diverse availability of silicon devices that can leverage the investment in RISC-V software across all conforming devices. This is only possible when building on a foundation of devices with guaranteed compliance with the specifications. Many RISC-V chips, systems and design flows will exploit the concept of custom instructions or other optimizations, delivering unique features. In these cases especially, the need to continuously test and confirm compliance throughout the design process becomes essential for all RISC-V based SoCs and systems. The technical issues of determining compliance with the RISC-V ISA are introduced with examples of customer extensions. The question of completeness and specification coverage are discussed and use cases of tool usage is provided. The Imperas experience of examining compliance on various proprietary RTL, open source RTL, FPGA, silicon, and ISS models will be explained with issues experienced being explained. A methodology to ensure continuous compliance during the development process from initial modeling, early RTL through final silicon will be shown.

1:40pm - 2:00pm 20 mins
Info
RISC-V Accelerators
The Esperanto ET-Maxion High Performance Out-of-Order RISC-V Processor
  • Polychronis Xekalakis - CPU Architect, Esperanto Technologies
  • Christopher Celio - CPU Architect, Esperanto Technologies

Location: 1st Floor, Exhibit Hall A-1

In this talk, we will present an update on ET-Maxion, a high frequency out-of-order RISC-V core which is being designed for TSMC's 7nm process. In the first part of our talk, we will describe its key micro-architectural features that allow it to achieve performance levels comparable to existing commercial high-end processors and discuss some of the design choices that we made. One such choice was the design of ET-Maxion as a core shielded against timing attacks such as Spectre and Meltdown. We will show that when such decisions are made early in the design process, they can be supported with negligible performance sacrifices. We will then share some of our experiences from implementing the RISC-V compressed instructions (RVC) and the weak consistency model (RV-WMO) in a superscalar out-of-order core, and present some of the design challenges we encountered. We will conclude our talk with a brief overview of our support for post-silicon debug and the performance monitoring improvements that we are planning to implement for ET-Maxion.

1:40pm - 2:00pm 20 mins
Info
Secure RISC-V
Never Again: Spectre-Proofing Chip Designs with End-to-End Formal Methods
  • Adam Chlipala - Associate Professor, MIT

Location: 2nd Floor Meeting Room 209/210

No one likes nasty surprises when microarchitectural optimizations combine to cause security problems, but how can we avoid those surprises without exhaustive consideration of all pairwise interactions between features in our chip designs? Formal methods provide a solution. Our team at MIT has been proving that concrete RISC-V designs avoid timing side channels, and the theorems apply to the end-to-end combination of hardware and software. For software implementations of widely used cryptographic algorithms, we prove that the timestamped history of signals on input and output wires is independent of changes to secret inputs. All proofs are checked algorithmically, so there is very little room for human error to endanger a security guarantee. We have designed a modular-decomposition strategy for security obligations, so that, for instance, each of a software program, a processor, and a memory system with caches can be analyzed separately. Then such components can be remixed to derive end-to-end theorems for new combinations with minimal new engineering effort. I will speculate (pun intended?) on how our initial results can scale to cover full-scale processors and reasonable mitigations to the Spectre and Meltdown attacks.

2:10pm - 2:30pm 20 mins
Info
Open RISC-V Platforms
Accelerating Inferencing on the Edge with RISC-V
  • Russell Klein - Technical Director, Mentor, A Siemens Company

Location: 2nd Floor Meeting Room 203/204

Machine-learning algorithms are highly compute intensive. Inferencing, which may be done on embedded systems (edge nodes), is less compute intensive, but certain applications such as real-time video image processing may stress the capabilities of even the fastest embedded processors. One way to address this problem is to move parts of the inferencing algorithms into accelerators implemented in hardware. 

This session will explore the use of high-level synthesis to create machine learning accelerators specific to an implementation to meet demanding power and performance goals. In traditional proprietary CPU architectures accelerators need to be accessed as peripherals. Much of the benefit of an accelerator is often lost through the time and energy needed to move the data in and out of the processor core. In contrast, RISC-V's open architecture allows developers to implement accelerators as more tightly integrated functions, as co-processors or even new instructions, delivering higher performance and lower power. This session will explore the impact of accelerators integrated into RISC-V cores in various ways.

2:10pm - 2:30pm 20 mins
Info
RISC-V Accelerators
Methodologies Behind the World's First RISC-V-based SSD Controller
  • Jihyo Lee - CEO & Co-Founder, FADU

Location: 1st Floor, Exhibit Hall A-1

This talk will showcase the design, methodology, and results behind the world's first RISC-V based SSD controller: the FADU Annapurna PCIe 3.0 X 4 NVMe SSD controller. The FADU Annapurna provides high throughput (3.5GB) and IOPS (800K), while consuming less than 1.8W active power. Powered by the FADU Annapurna, the FADU Bravo SSD is the first 7mm low-power U.2 supporting dual port and offers 3-4X IOPS / watt greater efficiency, 30% lower power, and the most consistent latency QoS in its class while only consuming 6-8W of active power. This talk will describe the innovative design, advanced flash memory controller system, and use of high-performance 64-bit embedded RISC-V Core IP that achieved this. The successful use of RISC-V IP has important implications for SSD development, particularly in future hyperscale datacenter applications. The adoption of RISC-V has positive implications for optimizing for small form factors and managing thermal and power constraints on advanced nodes for memory applications. FADU achieves this by the advanced and innovative architecture, extensive HW automation, flash acceleration, off-loading, and bypassing to be showcased in this talk.

2:10pm - 2:30pm 20 mins
Info
Secure RISC-V
How to Protect RISC-V Against Side-Channel Attacks?
  • Elke De Mulder - Embedded Security Researcher, Rambus
  • Michael Hutter - Senior Principal Engineer, Rambus

Location: 2nd Floor Meeting Room 209/210

Software implementations of cryptographic algorithms are vulnerable to Side-channel Analysis (SCA) attacks, basically relinquishing the key to the outside world through measurable physical properties of the processor like power consumption and electromagnetic radiation. Protected software implementations typically have a significant timing and code size overhead, as well as a substantially long development time because hands-on testing the result is crucial. Plenty of scientific publications offer solutions for this problem for all kinds of algorithms, but they are not straightforward to implement, as they rely on device assumptions which are rarely met, nor do these solutions take micro-architecture related leakages into account. 

We present a solution to this problem by integrating side-channel analysis countermeasures into a RISC-V implementation. Our solution protects against any first-order power or electromagnetic attacks while keeping the implementation costs as low as possible. We made use of state-of-the-art masking techniques and present a novel solution to protect memory access against SCA. Practical results are shown that demonstrate the efficiency of various cryptographic primitives running on our protected hardware platform.

2:40pm - 3:00pm 20 mins
Info
Open RISC-V Platforms
Command-Driven Data Transfer Protocols in RISC-V SoCs
  • Rajesh Vaidheeswarran - Director of Engineering and Sr. Principal Architect, Netronome

Location: 2nd Floor Meeting Room 203/204

There has been substantial interest in data transfer and synchronization protocols in RISC-V based SoCs. The Freedom series of SoCs use the Tile Link Protocol for cache coherence across CPUs and accelerators. CCIX and OpenCAPI are two other protocols that have received substantial attention and development effort. More recently, the Gen-Z protocol aims to provide memory-semantic access to shared storage. In this talk, we propose that high-performance multi-core systems with hundreds of cores may also need a third kind of data management protocol: programmer-managed bulk- and atomic-data transfers. The talk will demonstrate how workloads can benefit from such a protocol. Netronome has previously used such a protocol for on-chip data transfers in implementing high-performance coprocessors for networking. We will explore how this protocol can potentially be extended to intra-chip transfers in chiplet-based systems. We will also discuss potential changes to the RISC-V instruction set to enable programmer-managed data transfers. Finally, we will discuss how this protocol may be implemented over a popular link layer, such as PCIe.

2:40pm - 3:00pm 20 mins
Info
RISC-V Accelerators
Machine-Readable Specifications of RISC-V ISA
  • Alexander Kamkin - Leading Researcher, ISP RAS

Location: 1st Floor, Exhibit Hall A-1

In this talk, we discuss the use of machine-readable ISA specifications for creating verification tools for RISC-V microprocessors. Our team is working on the MicroTESK open-source verification framework. It uses machine-readable specifications in the nML language to automatically construct the following tools: an instruction set simulator, a test program generator, an online test program generator, and a binary code static analyzer. nML specifications describe registers, memory storages, addressing modes, and instructions' syntax and semantics. By the moment, the following RISC-V instruction subsets have been specified: RV32I, RV64I, RV32M, RV64M, RV32A, RV64A, RV32F, RV64F, RV32D, RV64D, and RVC. In total, the specifications cover about 250 instructions. The effort required to develop the specifications constituted about 4 person-months. The specifications can be easily modified to support more instructions (including custom extensions). The MicroTESK technology has been previously used to create TPGs for several RISC ISAs including ARMv8 and MIPS64, which have been successfully applied in industrial projects. The framework and the RISC-V ISA specifications are distributed under Apache License, Version 2.0.

2:40pm - 3:00pm 20 mins
Info
Secure RISC-V
SiFive TERP: A Trusted Execution Reference Platform for Embedded Secure Applications
  • Palmer Dabbelt - Engineer, SiFive
  • Nathaniel Graff - Software Engineer, SiFive

Location: 2nd Floor Meeting Room 209/210

The SiFive Trusted Execution Reference Platform (TERP) is an open source RISC-V reference architecture demonstrating a complete system which enables trusted execution of embedded security applications. The goal of TERP is to describe all the components necessary to build an embedded RISC-V processor which provides isolated multi-tenancy. We demonstrate that the resulting architecture is capable of supporting a wide array of target applications by evaluating multiple case-studies including operation of TERP as an asymmetric-key cryptography accelerator, a hardware random number generator, a Time-based One-Time Password (TOTP) token, a biometric identity verification card, and as a high-confidence command validation module. Finally, we have created a reference implementation of TERP as an FPGA image with firmware to demonstrate the use of TERP to build a USB hardware token for performing asymmetric-key cryptography.

3:00pm - 3:30pm 30 mins
Open RISC-V Platforms
Networking Break
3:00pm - 3:30pm 30 mins
RISC-V Accelerators
Networking Break
3:00pm - 3:30pm 30 mins
Secure RISC-V
Networking Break
3:30pm - 3:50pm 20 mins
Info
RISC-V Accelerators: Track 2
Introducing New 64GC IP in the SCRx Family of the RISC-V Compatible Cores by Syntacore
  • Alexander Redkin - Director, Syntacore

Location: 2nd Floor Meeting Room 203/204

We announce new 64bit IP in the SCRx family of the RISC-V compatible processor cores by Syntacore, including our second, high-performance 64bit Linux-capable design with SMP support. As always, newly introduced Syntacore IP are state-of-the-art clean slate designs in System Verilog, fully compatible with traditional EDA flows. In the session, we detail cores features, performance and collateral availability.

3:30pm - 3:50pm 20 mins
Info
RISC-V Accelerators
RISC-V Vector Performance Analysis
  • Guy Lemieux - CEO, VectorBlox Computing Inc.

Location: 1st Floor, Exhibit Hall A-1

We have implemented the RISC-V Vector Spec 0.5 in Spike for functional simulation, and completed an FPGA-optimized implementation for timing-accurate execution. Using several microkernel benchmarks suitable for embedded applications, individually optimized for each architecture, we evaluate the performance of the RISC-V Vector system compared to ARM NEON fixed-width SIMD instructions as well as VectorBlox variable-length vector extensions that have been optimized for use with the RISC-V base ISA. In addition to comparing performance, we investigate the individual architectural features and their area overhead so that we gain insight into the costs as well as the reasons why one architecture performs better. Current status: we have 3 benchmarks written, a Spike implementation, and a partial FPGA implementation of RISC-V vectors, and complete implementation of VectorBlox vector and NEON SIMD instructions. By the time of the summit, we expect to have ~10 benchmarks and a full FPGA implementation, as well as being up-to-date with the latest RISC-V vector spec available at that time.

3:30pm - 3:50pm 20 mins
Info
Secure RISC-V
Keystone: An Open-Source Secure Enclave for RISC-V Processors
  • Dayeol Lee - Graduate Student, UC Berkeley

Location: 2nd Floor Meeting Room 209/210

Hardware enclaves reduce the trusted computing base (TCB) by excluding complex system software, while also offering integrity, confidentiality, and remote attestation for isolated user-level processes. We present Keystone, an open-source hardware enclave implementation based on the RISC-V ISA. Keystone extends from the MIT Sanctum design and removes the requirement for non-standard hardware extensions by using standard RISC-V primitives including Physical Memory Protection (PMP). Keystone can be bootstrapped on an existing RISC-V core implementing the priv-1.10 specification, provided the uncore meets a few rudimentary criteria. We will demonstrate Keystone ported to a HiFive Unleashed board. While this work focuses specifically on memory isolation with trusted DRAM, Keystone can be easily adapted for a variety of threat models including untrusted DRAM or microarchitectural side-channel attacks. Importantly, Keystone is fully open-source, and thus a compelling building block for secure system design.

3:55pm - 4:25pm 30 mins
Info
RISC-V Accelerators: Track 2
Ara: 64-bit RISC-V Vector Implementation in 22nm FDSOI
  • Fabian Schuiki - PhD Student, ETH Zurich
  • Matheus Cavalcante - PhD Student, ETH Zurich

Location: 2nd Floor Meeting Room 203/204

In this talk, we detail our experience in the design and implementation of the RISC-V Vector Extensions (v0.4 draft) in an advanced silicon process. Ara is a high-performance vector co-processor soft core that attaches to and cooperates with an existing open-source RISC-V core Ariane, implementing RV64. Ara receives instructions from Ariane, which splits the instruction stream into scalar and vector parts. The vector processor instance that we implemented in silicon features four lanes, with floating-point units, a 64 KiB register file with dynamic vector length and count, independent load/store units, and has hardware to accelerate common vector reductions, such as vector summation and inner product. Two variants of the Ariane+Ara duo are combined with memory into a system-on-chip, aiming at exploring both the high-performance and low-power ends of the silicon implementation spectrum. We discuss design implementation insights, lessons learned, and tradeoffs; and we present area, performance, and power results in Globalfoundries' 22FDX FDSOI process.

3:55pm - 4:15pm 20 mins
Info
RISC-V Accelerators
Design and Implementation of a RISC-V ISA-based In-order Dual Issue Superscalar Processor
  • Libin TT - Principal Engineer, C-DAC
  • S. Krishnakumar Rao - Associate Director, C-DAC

Location: 1st Floor, Exhibit Hall A-1

This session details the microarchitecture design of an 11-stage pipelined RISC-V ISA based 64-bit processor, VAJRA64. The microarchitecture of fetch, decode and execute stages are detailed. RISC-V is a new instruction set architecture (ISA) that was originally designed to support computer architecture research and education developed by University of California, Berkeley and has been open sourced as BSD license. 

3:55pm - 4:25pm 30 mins
Info
Secure RISC-V
Establishing a Security Verification Framework For The RISC-V Architecture
  • Jason Oberg - CEO, Tortuga Logic

Location: 2nd Floor Meeting Room 209/210

Today, there is a preponderance of popularity and support toward using open-source instruction set architectures such as RISC-V and their respective hardware designs due to their customizability and the ability to collaborate on successful designs. Along with these benefits, open-source hardware designs have the unique opportunity to have their microarchitectural features enhanced in a variety way of ways to improve performance. However, recent microarchitectural security exploits (such as Spectre and its variants) demonstrate that microarchitectural performance features have a dramatic impact on system security. The open-source nature of RISC-V presents an opportunity to add microarchitectural features in a secure manner without compromising performance by leveraging a Secure Development Lifecycle (SDL). In order to create a successful SDL for open-source hardware designs, several challenges need to be addressed. 

In this talk, we discuss the state of hardware security in general, then discuss the unique security opportunities and challenges in open-source hardware design. Also, we will present a framework and set of techniques and methodologies for understanding the security ramifications of any microarchitectural/architectural change that is applied to a design. Lastly, we will present an example security analysis on a real world hardware design using these techniques.

4:30pm - 5:00pm 30 mins
Info
Secure RISC-V
Secure Bootstrapping of Trusted Software in RISC-V
  • Ilia Lebedev - Graduate Student, Massachusetts Institute of Technology

Location: 2nd Floor Meeting Room 209/210

A growing concern with the diverse RISC-V ecosystem is the proliferation of security primitives which do not straightforwardly compose into secure systems. We must address this issue by creating reusable, well-understood fundamental primitives for security. One often overlooked aspect of a secure system is the process by which its trusted environment is initialized. 

In this session, we discuss a secure boot procedure for a generic RISC-V processor system, one which endows a software environment with a cryptographic key pair for remote attestation, and a certificate with a cryptographic measurement of the boot image. This protocol can be used to measure and sign arbitrary software, is agnostic of hart implementation and ISA features, is appropriate for a multi-hart system (provided inter-hart interrupts are available), and executes entirely in M-mode (does not rely on hardware-assisted privilege). We rely on standard software cryptographic primitives throughout the secure boot process, namely SHA-3 hashes, ed25519 elliptic key cryptography, and an AES-256 cipher. After boot, the software system is trusted to maintain confidentiality of its secret keys, although a malicious boot image does not compromise the keys of an honest one. We discuss several mechanisms for deriving trusted device keys (commitment to a nonce, non-volatile memory, physical unclonable function), and outline how this secure boot process is used in the Sanctum and Keystone secure processors. We also discuss a work-saving technique to improve boot latency by caching encrypted keys in untrusted memory. A C and machine code implementation of this secure boot protocol is provided as open-source software, unencumbered by licenses or patents. We also demonstrate an instance of this secure boot protocol in the context of the Sanctum processor.

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