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Poster Sessions Tues, Dec 10

Stop by the Gallery to view and discuss the work of your colleagues in this informal, relaxed setting. 

For Wed, Dec 11 poster sessions, please click here


Achieving Fault Tolerance For Persistent Memory

11:30 a.m. - 1:30 p.m.

3:30 - 5:30 p.m. 

Data-intensive applications such as machine learning and data analytics demand high capacity of main memory for high performance. However, building a system with large amount of volatile DRAM is expensive and the system does not scale beyond a single machine. Recent advances in memory technologies, termed persistent memory, offer performance close to DRAM but could cost significantly less make it feasible to replace several tiers of the memory hierarchy. However, to make large-scale persistent memory deployments practical, memory system designers will first need to solve the problem of how to guard against unavoidable wear-out and failures.  We propose a novel approach to providing fault tolerance for persistent memory. Our key insight is to treat memory as a distributed shared memory system and rely on a consensus protocol to keep the replicas consistent. Although consensus protocols have been historically considered a performance bottleneck, several recent projects have demonstrated a promising new approach to achieving high-performance consensus. Our initial experiments using an emulator of memory controller demonstrate reasonable overhead over local memory access and show great promise for persistent memory as scalable main memory. We are working on attaching the fault tolerance persistent memory with RISC-V over OmniXtendTM cache coherent fabric.

Presenter: Huynh Tu Dang, Principal Engineer, Western Digital 

Open-source Validation Suite for RISC-V

1:30 - 3:30 p.m.

5:30 - 7 p.m.

In this talk, we propose a validation suite, applicable for different RISC-V designs. The suite can be considered as a stack of the following three layers: test programs in the Assembly language, test templates to describe how to get more test programs, and MicroTESK framework set up by RISC-V specifications in the nML and mmuSL languages to process test templates. The approach has been used for verification of different RISC ISAs, and currently it is applied for testing of RISC-V SCR1 core by Syntacore. MicroTESK can be also used for binary code deductive analysis. The whole suite is an open-source solution and distributed under Apache License, Version 2.0.

Presenter: Alexander Kamkin, Senior Researcher, ISP RAS; Mikhail Chupilko, Senior Researcher, ISP RAS

Experiments and AI Model Validations for Neo/TVM on RISC-V Architectures with SIMD

11:30 a.m. - 1:30 p.m.

3:30 - 5:30 p.m.

TVM, as a open deep learning compiler stack for neural network models, for multiple hardware backends such as CPUs, GPUs, and specialized accelerators. The service, Amazon Sagemaker Neo, uses TVM to enhance deployment performance for AI applications.  Being used as fall-back engine for AI computing, RISC-V with two vector construct proposals, Superword vector (V) and Subword SIMD vector (P) instructions, has been proposed.  In this work, we build on our previous work in the enabled flow for the TVM flow and stack on RISC-V with SIMD instructions, to report further optimization flow such as quantization flow and the performance flow with the LongShort-Term Memory (LSTM) models.  In addition, we are currently working on the validations of the software flow of Neo/TVM on RISC-V with SIMD for Gluon/MXNET Model Zoo.  Experiments show that our flow with P extension achieves 2.4x on LSTM, 2.5x on LeNet, and 2.1x on AlexNet, respectively, with AndeSim simulator running RISC-V with P extension compared to RISC-V on 16 bit integer without SIMD.

Presenter: Allen Lu, Professor, Peakhills Group Corporation; Jenq Kuen Lee, Professor, National Tsing Hua University, Taiwan 

Designing RISC-V Custom instruction extensions with timing driven profile and analysis

1:30 - 3:30 p.m.

5:30 - 7 p.m.

IoT and Automotive applications require secure updates and device management. By extending the RISC-V capabilities Cerberus are adding custom hardware to support accelerated and tamper proof encryption together with key management functionality for software updates and remote device management. Using application software as the starting point new custom instructions are profiled and analysed including approximate timing simulation. On-going software optimizations are assisting in further design exploration, which is modeled in parallel to the RTL development. Throughout the design cycle the needs for compliance and verification are essential to enabling innovations around the open RISC V architecture. Open source processor models have many advantages; however, one important area of concern is the risk of unintended consequences to the base operation when adding architectural extensions to a model. Modular and container approaches are safeguards to be considered as a fundamental guideline when designing models of the extensions to the RISC-V ISA. In addition, options to support extensions need to be facilitated within the model infrastructure to allow analysis of the new extensions to be efficiently tested and profiled. All with continuous testing for compliance throughout the development process.

Presenter: Jim Straus, Sr. Consulting Engineer, Imperas Software

Building Mixed-Criticality Systems with RISC-V-based SoC FPGAs

11:30 a.m. - 1:30 p.m.

3:30 - 5:30 p.m.

As embedded and Internet of Things (IoT) applications for the automotive, aerospace, and medical industries tend to consolidate an ever-growing number of software stacks with a diverse set of features and requirements, these applications are becoming increasingly dependent from mixed-criticality systems (MCS). While the legacy approach to manage integration tend to segregate each subsystem into an independent computing unit (i.e., federated architectures), the increasing pressure to minimize the SWaP-C (size, weight, power, and cost) budget has pushed the Industry to a clear paradigm shift towards consolidation onto single high-performance computing units (HPCU). A great example of an HPCU available soon in the RISC-V ecosystem is the Microchip PolarFire SoC FPGA, which provides a high degree of performance and flexibility by offering a rich set of heterogeneous ‘hard’ processors complemented by a ‘soft’ reconfigurable fabric.  In this talk, we start by examining the PolarFire SoC’s architecture and explaining why this hardware platform is a perfect match to tackle the mixed-critical requirements of modern embedded and IoT applications. We then share our experience in building the most complete commercial-graded software stack to date for RISC-V-based MCS: MultiZone TEE provides a set of secure enclaves for security-critical operations and secrets, FreeRTOS provides a real-time environment to safely meet strict deadlines, and Linux provides a rich execution environment for friendly user interfaces and connectivity. Lastly, we describe a use case for the Industrial IoT, by demonstrating how to safely and securely operate a robotic arm via a remote connection.

Presenter: Sandro Pinto, Professor, Hex Five Security Inc.; Tim Morin, Director of Product Marketing, FPGA Business Unit, Microchip Corporation 

RISC-V ISA Extensions for Efficient Acceleration of IoT Applications

1:30 - 3:30 p.m.

5:30 - 7 p.m.

Extend the existing RISC-V ISA for efficient support of edge and IoT computing. Also present the optimization techniques from compiler's perspective.

Presenter: Weifeng Zhang, Chief Scientist of Heterogeneous Computing, Alibaba Group 

SHAKTI E-class SDK and IDE for IoT Applications

11:30 a.m. - 1:30 p.m.

3:30 - 5:30 p.m.

The SHAKTI processor program, an initiative from RISE Lab IIT Madras, aims at creating open source processors as well as an ecosystem that includes software tools, supporting IPs and peripherals. Such an ecosystem will enable rapid adoption of the RISC-V processor by the research and industrial community. The SHAKTI project is building a family of 6 processors, based on the RISC-V ISA. The SHAKTI E-class from this family is aimed at automotive and Internet of Things devices. The E-class is an In-order 3 stage 32/64-bit micro-controller supporting a subset of RISC-V ISA. It is designed with the goal of low area and power consumption, which is suitable for use in IoT devices and systems that have operational frequency of less than 200 MHz on silicon. In this showcase session, we will present the Software Development Kit (SDK), and the SHAKTI Integrated Development Environments (IDEs), the debugger for the SHAKTI E-Class processor using which IoT applications can be developed. Few applications such as automatic thermostat controllers, and use of IDEs for building IoT devices with various sensors will be presented to demonstrate the capability of the low power E-class processors.

Presenter: Arjun Menon, Senior Project Officer, RISE Lab, Indian Institute of Technology Madras; Anand Kumar, Senior Project Officer, RISE Lab, Indian Institute of Technology Madras 

Application Optimization and Status Update of RISC-V P Extension

1:30 - 3:30 p.m.

5:30 - 7 p.m.

The RISC-V P (DSP) extension task group is formed in August 2018. The chair of the task group is Chuan-Hua Chang from Andes Technology. The co-chair of the task group is Eric Flamand from GreenWaves Technologies. The charter of the P extension task group is as follows:  Define and ratify Packed-SIMD DSP extension instructions operating on XLEN-bit integer registers for embedded RISC-V processors. The TG will also define compiler intrinsic functions that can be directly used in high-level programming languages.  This talk will be focused on reporting the use of the P extension instructions to optimize various applications and library functions, such as audio codec, neural network inference applications, or complex multiplication, filtering functions, etc.  And this talk will also report on the progress and the current status of the P extension task group regarding designing the extension and the issues discussed and determined by the task group participants.  Some P extension instruction usage analysis will be given in the talk. And more performance data on general DSP functions and various applications will be given as well to help determine the usefulness of the proposed instructions.

Presenter: Chuan-Hua Chang, Senior Director of RD/Architecture Division, Andes Technology Corporation 

An Open and Coherent Memory Centric Architecture Enabled by RISC-V

11:30 a.m. - 1:30 p.m.

3:30 - 5:30 p.m.

There is a dearth of interfaces for efficient attachment of emerging non-volatile memory and purpose-built compute accelerators to processor pipelines. Early integrated microprocessors exposed an off-chip front-side bus to which discrete memory and peripheral controllers could attach in a standardized fashion. With the advent of symmetric multiprocessing and deep caches, this direct connection, together with memory controllers, has been implemented primarily using proprietary on-die technology. Proprietary interconnects and protocols hinder architectural innovation and are at odds with the open nature of the rapidly growing RISC-V movement. In this talk we introduce OmniXtend, a fully open coherence protocol meant to restore unrestricted interoperability of heterogeneous compute engines with a wide variety of memory and storage technologies. OmniXtend was motivated by the desire to break out of the status quo of prevailing system design and fueled by the urgent need of the RISC-V ecosystem for a common scale-out protocol. Our proposed system supports a four-hop MESI protocol and is designed to take advantage of a new wave of Ethernet switches with stateful and programmable data planes to facilitate system scalability. We briefly discuss the protocol operation and show performance measurements of the first ever NUMA RISC-V system prototype.

Presenter: Paul Loewenstein, Director, Western Digital

Gaining the Upper Hand in the Escalating Cyberwar

1:30 - 3:30 p.m.

5:30 - 7 p.m.

In today's war against cybercrime, things are going from bad to worse. To gain the upper hand, we need to change the battlefield. Our systems need a way to know that they are being attacked. They also need to be able to prevent an attack from doing any damage, and run applications that when being attacked can adapt in real-time. In this presentation, we will demonstrate how applying instruction-level correctness to a RISC-V processor makes gaining this upper hand a reality. Instruction-level correctness ensures processors only execute instructions that are consistent with the developer's intended system behavior. This means that when an embedded system is asked to do something that it shouldn't, it will immediately know that it is under attack and be able to stop the violating instruction from executing before any damage is done. We will show how an application can respond to different types of cyberattacks with the appropriate violation response. For example, we will look at how an attacked application can force the system to restart, ask for user input, turn on logging to gather data about the attacker, scramble memory, or activate an alternate safe application that stops listening to the network.

Presenter: Greg Sullivan, Co-Founder & Chief Scientist, Dover Microsystems

Architectural Overview of the European Processor Initiative

1:30 - 3:30 p.m.

5:30 - 7 p.m.

The European Processor Initiative (EPI) is a project currently implemented under the first stage of the Framework Partnership Agreement signed by the Consortium with the European Commission, whose aim is to design and implement a roadmap for a new family of low-power European processors for extreme scale computing, high-performance Big-Data and a range of emerging applications. The project aims to deliver a high-performance, low-power processor, implementing vector instructions and specific accelerators with high bandwidth memory access. The EPI processor will also meet high security and safety requirements.

The EPI Common Platform (CP) architecture is organized around a 2D-mesh Network-on-Chip (NoC) connecting computing tiles based on high-performance general-purpose CPU core with built-in FPU acceleration and specialized application-accelerators with different acceleration levels designed within EPI project. A common software environment between heterogeneous computing tiles will harmonize the system as well as acting as a common backbone of IP components for IO connection with the external environment such as memories and interconnected or loosely coupled accelerators. With this CP approach, EPI will provide an environment that seamlessly integrates any computing tile. The right balance of computing resources for application matching will be defined through the ratio of the accelerator and general-purpose tiles.

EPI is developing processor IPs based on the RISC-V Instruction Set Architecture, providing power efficient and high throughput accelerator tiles within the GPP chip. Using RISC-V allows leveraging open source resources at hardware architecture level and software level, as well as ensuring independence from non-European patented computing technologies. The EPAC basic building block is a tile containing up to 8 vector processors and specialized units. The processors are coherent, sharing L2 cache banks through a Network-on-Chip, each bank with its associated Home Node agent. through a Network-on-Chip. The processors will support RISC-V vector instructions, and will also control the specialized units dedicated to Stencil and Deep Learning acceleration. The vector and stencil capabilities will address HPC workloads, while the Deep-Learning units will target AI applications.

Presenter: Nick Kossifidis, Principal Research Engineer, ICS-FORTH

For Wednesday, December 11 poster sessions, please click here.