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Poster Sessions Wed, Dec 11

Stop by the Gallery to view and discuss the work of your colleagues in this informal, relaxed setting. 

For Tues, Dec 10 poster sessions, please click here.

The RISC-V in Implantable Medical Devices

11:30 a.m. - 1:45 p.m.

Implantable medical devices (IMD) include I-V stimuli sources, electrodes connected to tissue, sensors, amplifiers, complex transceivers, and a CPU controlling everything. The main specific characteristics of IMD ASICs are: implemented in HV-CMOS technology to handle high voltage stimuli (e.g. up to 20V); micropower consumption; reliable and safe but complex circuits and systems; and a very low volume production (thousands to hundreds of thousands) to share the cost of the ASIC development. Thus, an open source, scalable CPU like RISC-V would be helpful to allow small to large companies to develop their own ASICs. First, the case of IMDs will be presented including state of the art and industry overview. The main characteristics of IMD ASICs are discussed (technical, engineering, business point of view). Then a RISC-V core targeting medical devices is presented. The core was designed in a 0.18µm HV-CMOS process combined with several biological tissue stimuli and sensing circuits.  The CPU was optimized for area, and power consumption. The complete test chip (analog+RISC-V) occupies a 5mm2 area but only 0.82mm2 correspond to the RISC-V core, which operates up to 20MHz, with energy needs of less than 34 pJ/cycle. As far as we know this the first RISC-V aimed at medical applications proposed.

Presenter: Alfredo Arnaud, Dr.Eng, Professor, Universidad Católica del Uruguay; Alfonso Chacón Rodríguez, Dr. Eng, Professor, Instituto Tecnológico de Costa Rica 

RISC-V Compliance Suite: Ensuring Maximum Software Reuse with Device Compatibility, the Defining Quality Test for a RISC-V Processor

11:30 a.m. - 1:45 p.m. 

RISC-V Processor Verification  Co-Authors:  Lee Moore, Imperas, RISC-V compliance task group contributor. Allen Baum, Esperanto, chair RISC-V compliance task group. Stuart Hoad, Microchip, co-chair RISC-V compliance task group.  Abstract: The RISC-V ISA is an Open specification which permits extensions beyond the base structure, this flexibility is the defining characteristic of RISC-V. A fully tested and verified core is always a design objective, but compliance ensures compatibility with other devices. Compliance is not just an academic requirement as the complete ecosystem is built on a foundation of compatibility that stimulates adoption, investment and software reuse.  The first step for any project is to run the latest compliance suite. This is not just a topic for core IP developers, due to the extendibility and flexibility of RISC-V any user will need to ensure modifications or extensions are both compliant and did not perturb the original verified core deliverables. Free Open Source cores have an attractive price, compliance testing is an essential part of the process to establish it's a good deal.  Latest updates on the status of the ready-to-use compliance suite and discussion of plans for the new Vector and Bit Manipulation extensions plus the first public release of the results of cores passing the latest test suites.

Presenter: Lee Moore, CPU Architect, Imperas Software

Integrating RISC-V Instruction Set Simulator (ISS) with SystemC

11:30 a.m. - 1:45 p.m.

In this presentation we will talk about integrating RISC-V ISS with SystemC and effectively using it in Virtual Prototype of SoC for the purpose of embedded software development.  Virtual prototype is a fast simulation model of the hardware system that provides an environment where the target platform binary can be run as-is, at speeds comparable to hardware speeds, using the same development environment.  SystemC based virtual prototype of SoC & Electronics Systems are increasingly being used for setting up advanced methodologies for development & testing of embedded software.   While RISC-V ecosystem is in nascent stage, there is widespread interest in the industry to explore the usage of RISC-V for various use cases. People have started feeling the need for SystemC modelling infrastructure for RISC-V ecosystem. For developing the Virtual Prototype of an SoC, we need to develop the SystemC / TLM2.0 models of various IP blocks of SoC and connect these with the CPU model through bus model.  There are various Instruction Set Simulators (ISS) available for RISC-V, few of these as listed below: 

  • \tSpike Simulator 
  • \tSwerV ISS from Western Digital 
  • \tQEMU 

The RISC-V ISA being open source, lots of development in the ecosystem in being driven through the community work, and we can expect that more such ISS are likely to be developed.  These ISS are purely functional model of the CPU, and very much suitable to be used in the Virtual Prototype of SoC for embedded software development. To use an ISS in SystemC based Virtual Prototype, we need to integrate the ISS with SystemC. In this talk we cover how to integrate an ISS with SystemC. The SystemC wrapper on RISC-V ISS should have the following minimum set of features: ISS to act as TLM2.0 Master should have a TLM2.0 master socket, through which RISC-V CPU should be able to access the memory map of SoC i.e. peripherals, memory, DMA etc. Some part of memory map may be inside ISS itself (for internal components like boot ROM, CLIC etc..). We need to add configurability in the wrapper, through which user can specify which addresses should go to internal memory and which address should go to TLM2.0 socket. Pins for Interrupts ISS should have sc_in pins for interrupts. Synchronization between ISS & SystemC Kernel. An ISS executes the cross compiled code. It fetches instructions one at a time and executes them. By default, ISS will keep on executing the code from start to end, and SystemC will not get control to run the SystemC models in the virtual platform. We need to break the default sequence of ISS to call wait() at right points, so that SystemC kernel gets control. 

In this talk we will also discuss how to develop the basic setup for validating the SystemC- ISS integration. At CircuitSutra, we have integrated Spike simulator with SystemC and effectively used that in Virtual Platforms. This work will be the basis of the presentation. We are also in the process of integrating SwerV ISS (from Western Digital) and QEMU RISC-V model with SystemC. Objective is to come up with a unified methodology and a common SystemC interface for CPU model, so that users can use any of the available ISS in plug and play manner without having to change the code for their virtual platform. This can also be used to develop highly robust verification environment, where multiple ISS can be used as reference models to verify the CPU.

Presenter: Umesh Sisodia, SMTS, Circuitsutra Technologies Pvt Ltd; Sudhanshu Tripathi, SMTS, Circuitsutra Technologies Pvt Ltd 

A Vehicle Security Surveillance System Based on a RISC-V Processor

11:30 a.m. - 1:45 p.m.

Vehicle break-ins have reached an epidemic level in recent years in some urban areas. This criminal activity which typically involves breaking vehicle windows and stealing personal properties inside the vehicle only takes a few seconds to complete, however, it can cause a significant property loss and even identity theft. In this paper, a parking mode security surveillance system that deters and records the vehicle break-ins is proposed. This system takes advantage of the state of art of internet of things and artificial intelligence technology, making it perform more proactively than traditional shock sensor-based or motion detection-based vehicle security alarm. A low-cost and low-power consumptive RISC-V system which contains basic video/audio signal neural network processing units can serve well in this application.

Presenter: Shaomin Xiong, Director, Western Digital; Toshiki Hirano, Director, Western Digital

The RISC-V Orbital Space Lab Satellite Payload based on a Fault-Tolerant Processor Core with Hardware Thread Full/Weak Protection and Thread-Controlled Watch-Dog Timer

11:30 a.m. - 1:45 p.m.

This presentation addresses the first RISC-V space laboratory called RISC-V Orbital Space Lab (ROSLAB-V) and the first space-qualified PULPino-compatible Klessydra core version designed to manage an orbital laboratory. Since the electronic devices which operate in the harsh space environment require a high grade of reliability a fault-tolerant architecture is required in order to cope with the severe environment requirements as well as with resource availability. To test and study new fault-tolerant techniques an orbital test laboratory called ROSLAB-V has been developed. The ROSLAB-V board is equipped with an Artix-7 FPGA and it has been designed to be programmed via Over-the-Air (OTA) update. The ROSLAB-V is equipped with a Quad-SPI Flash memory, partitioned to use the 7 series FPGAs Fallback MultiBoot feature. It has been designed to test multiple design with a single OTA update. The first microprocessor that has been designed to managed ROSLAB-V is a compact variant of the Klessydra F03x microcontroller soft core family named F03x_mini. This core is RV32I compliant fault-tolerant multithreaded architecture, enhanced by a TMR-based full-weak HART protection and a Thread-Controlled Watch-Dog Timer (WDT) module, and it will be the fallback design to which that the FPGA automatically reload in case of non-recoverable error.

Presenter: Francesco Vigli, Digital Hardware Designer, AizoOn Group

Pre-silicon Detection of Hardware Trojans and Security Vulnerabilities in RISC-V Cores

11:30 a.m. - 1:45 p.m.

Processor cores provide a fertile soil for the insertion of hardware Trojans. Complex pipeline implementations chasing performance, power, and area targets are a great hiding place for malicious logic. They also create a vast space of functional corner-cases, resulting in even advanced verification flows to routinely miss bugs. While certain bugs may not affect the intended use cases, they could be leveraged to device misuse cases for nefarious purposes. The goal of this presentation is to increase awareness of these types of risks. We present concrete examples of how stealthy Trojans could be inserted in RTL code. Undocumented, custom instructions, and FSM modifications that do not required additional state bits are some examples. We show how these Trojans could be leveraged as kill switches, or to escalate privileges, for example. In addition, we also discuss how certain corner-case behaviors, causing unnecessary memory accesses, for example, should be either avoided or considered carefully, even when they have a negligible effect on performances. Experiences of detecting security-relevant issues in open-source RISC-V cores, including the Rocket core, are presented.

Presenter: Sven Beyer, Hardware Verification Engineer, Edaptive; Blake Buschur, Product Manager Design Verification, Edaptive 

Graphics Processing Extension RISC-V

1:45 - 4:00 p.m.

Traditionally GPUs (Graphics Processing Units) have focused on high performance use cases such as gaming, computer vision and machine learning. These GPUs often use programming languages separate from what is used on the CPU.  Currently, very few hardware options for graphics processing exist at the low end. Options available often additionally suffer from proprietary programming languages or function calls. Many use cases are believed to exist at the low end such as Kiosks, Billboards, Casino Gaming, Toys, Robotics, Appliances, Wearables, Industrial HMI, Infotainment, and Automotive Gauge Clusters. These use cases use retrofitted SoCs borrowed from other markets.  A RISC-V ISA extension for 3D graphics would resolve many ecosystem problems while promoting the creation of new use cases and end products. The same programming language could be used on both the CPU and GPU. The GPU should be scalable similar to what has been seen in RISC-V processor cores and can be optimized for specific graphics and accelerated computing needs as a result. The ISA extension for the GPU can be integrated into the compiler to optimize computations without effort from the developer. These considerations will be explored and a proposal for a new working group will be considered.

Presenter: Atif Zafar, Director of International Marketing, Pixilica; Grant Jennings, Director of International Marketing, GOWIN Semiconductor 

JIT Superoptimization on RISC-V via Symbolic Execution

1:45 - 4:00 p.m.

We present a dynamic-language JIT in which the backend is automatically inferred from the formal ISA specification and the formal semantics of the VM's Intermediate Language.  The core of the JIT comprises a Symbolic Execution Engine, and a Search Engine.  The SEE computes the algebraic effect of an instruction sequence on an input state given as symbolic variables; whereas the instruction sequence itself is also given algebraically.  (This latter fact is crucial because in a JIT, the binary program text is not known ahead-of-time, making many known IL lifting algorithms inapplicable.) Based on CLP(FD) algorithms, the Search Engine traverses the space of instruction sequences to find a sequence whose effect unifies with the effect of the VM bytecode being translated.  To the found sequence, the search procedure attaches the proof of its equivalence with the VM bytecode.

Presenter: Boris Shingarov, VM Designer, LabWare

RISC-V Based Security Co-Processors for Mission Assurance Architecture

1:45 - 4:00 p.m.

MIT Lincoln Laboratory has developed a Lincoln Asymmetric Multicore Processing (LAMP) architecture for mission assurance, which provides two physically separated partitions with different complexities, criticality, and levels of trust. As the trusted partition is a root of trust and recovery, its processing cores and applications must be properly tailored and optimized so that users can reason about, validate, verify, and thus trust them. We have leveraged the RISC-V architecture for the development of a trusted security co-processor for the trusted partition. The open RISC-V instruction set architecture, with non-restrictive micro-architectural and design choices, has enabled us to extend the conventional performance oriented design space to include a new security dimension. Our design approach considers the mission objectives encountered throughout the system's life cycle, essential system functions and resources, and potential vulnerabilities and mitigations to develop a set of system requirements and security metrics.  Security features can thus be included and evaluated even at the processor design phase. A functional and security co-design environment has been created to efficiently customize and optimize in a design space consisting of hardware, software, performance, and security. A test case of a security co-processor used to secure a legacy industrial control system has been developed to evaluate the benefits to the system's overall security and mission readiness.

Presenter: Donato Kava, Associate Staff, MIT Lincoln Laboratory; Alice Lee, Associate Staff, MIT Lincoln Laboratory 

Trustworthy Systems: From The ISA On Up

1:45 - 4:00 p.m.

For a system to be *trustworthy* there must be good reasons to declare it trusted. Trustworthiness has many dimensions and must be considered at all layers of a system. The extensible RISC-V ISA affords an opportunity for assuring trustworthiness from the hardware on up.  RISC-V can be extended with Capability Hardware Enhanced RISC Instructions (CHERI) to provide strong, fine-grained, capability-based security at the lowest layer of the hardware/software stack. The formally verified, open source, Syracuse Assured Boot Loader Executive (SABLE) demonstrates capability-based secure/trusted boot. The formally verified, open source, seL4 microkernel strictly enforces capabilities in a production grade, modern, high performance Operating System (OS) kernel. The open source Genode OS framework and Sculpt OS leverage capabilities to enable a componentized software architecture. Genode also supports concurrent use of diverse VMMs to compose arbitrary mixed trust systems with strong isolation of VMs. All the foregoing can be remotely attested as part of an Attestation, Authentication, Authorization, Access Control, Accounting, Attribution, and Audit (AAA) framework, offering defense in depth, assured by design, independently verified by formal analysis and penetration testing.  This and other approaches to achieving system trustworthiness benefit from the downward extensibility to hardware facilitated by the RISC-V ISA and community.

Presenter: Adam Wiethuechter, Chief Scientist, Critical Technologic Inc.; Stuart Card, Chief Scientist, Critical Technologies Inc. 

On the seL4 Center of Excellence

1:45 - 4:00 p.m.

seL4 is the first formally verified microkernel, which offers fundamental software separation properties and provides new opportunities to build assured computer systems. The goals of the seL4 Center of Excellence include maturation of seL4 technology, stabilization of the software distribution, training and expanding the user base, and developing much needed capabilities required by the Department of Defense, other government agencies, and commercial applications.  The formal verification of seL4 on RISC-V, which is set to be completed by Data61 soon, has made various members of the Center of Excellence interested in the combination of RISC-V and seL4. We collectively hope to make RISC-V based systems a part of the Center of Excellence software distribution, and foster further adoption of both technologies.

Presenter: Adam Wiethuechter, Chief Scientist, Critical Technologic Inc.

For Tuesday, December 10 poster sessions, please click here.