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Be a Speaker at the RISC-V Summit 2019!

RISC-V is fast gaining support as a fully open and extensible instruction set architecture. We are seeking proposals for papers for the second RISC-V Summit, to be held in Santa Clara, Dec.9-12 2019.

Guided by Leaders in the Industry

The program for the RISC-V Summit is under the guidance of established academic and industrial leaders in the Computer Architecture field.

Program Chair:  Prof. Borivoje Nikolic, UC Berkeley
Vice Chair: Dr. Zvonimir Bandic, Western Digital Corporation

Committee Members
Simon Davidmann, CEO, Imperas
Cesare Garlati, Founder, Hex-Five Security
Dr. Richard Ho, Principal Engineer, Google
Dr. Yunsup Lee, CTO, SiFive
Gajinder Panesar, CTO, UltraSoC
Zdenek Prikryl, CTO, Codasip

What We’re Looking For ...

We’re seeking proposals for speaking sessions at the second RISC-V Summit Dec. 9-12, 2019, exploring recent developments in the RISC-V community.

RISC-V is fast gaining support as an attractive license-free approach to architecture, with the potential to disrupt the microprocessor IP market. The conference program will explore this open standard collaboration, providing opportunities for participants to learn about its benefits,  current and prospective RISC-V projects and implementations, technical capabilities and the commercial and strategic implications of the technology.

The speaking lineup and program are selected based on the topic/content submitted and the speaker’s qualifications by the advisory board.

Contact information for the primary speaker must be included. As part of our vetting process, we will need to follow up directly with the speaker on the submission and/or their background and expertise. Submissions without speaker contact information will not be considered.

Before Submitting Your Proposal

Submission Guidelines
  • Is the submitted speaker considered a thought leader and/or is knowledgeable on the topic? 
  • Can the speaker go beyond the surface of a topic and provide in-depth education?

  • Is the submitted topic unique / fresh? Information that cannot be found in another conference or format? (In other words, please do not submit the same session you have already presented at another conference without substantial updates.)

  • Is this session a real-world case study? If submitted by a vendor, does it include the customer as a speaker?

  • Is this session based simply on theory or contain actionable, practical information that attendees can put in practice?
  • Is it controversial? Our goal is to provide a forum where attendees can learn about cutting edge topics and get advice and straight talk on the evolution of RISC-V technology.

  • Technically solid. Is the content technical and deep enough? Does it go beyond a high-level overview.

  • Business-focused. Does the talk connect business goals with technology needs.

  • Is it just a marketing / sales pitch? If so, it won't be accepted in the conference program.

  • RISC-V cores, from small 2-stage cores to out of order high performance
  • FPGA optimized RISC-V cores
  • Advances in compilers (glibc, LLVM), toolchains for RISC-V including debuggers and tracers
  • Advances in open source design tool flow: RTL simulators, design verification, and synthesis/place and route
  • Linux operating system support: block IO, virtualization, desktops
  • Automotive and Internet of Things applications
  • Security architecture applications: secure enclaves, secure execution, Spectre and Meltdown defense mechanism proposals
  • Neural network inference acceleration applications and software integration
  • RISC-V in education: from cradle to grave
  • Benchmarking CPU cores

Topic not listed? Submit your novel idea!

Format and Types of Session Sought


(1-2 speakers)

Talks/Lectures are case studies or issue-oriented presentations on original research, groundbreaking ideas, or insights on future trends. Sessions should provide concrete examples, and contain both practical and theoretical information. No sales pitches, product launches/announcements. 


Showcases are sessions focused around product announcements and ecosystem developments for the organizations driving the development of RISC-V technology.


Panels are 45-minute sessions, during which 3- 4 panelists participate in a moderated discussion on a specific topic or theme. Panelists should offer differing viewpoints or experiences to help foster a dynamic discussion. Panel submissions should only list panelists and a moderator that have confirmed their participation within the proposal.


Tutorials may be interactive/hands-on and the focus is on education/training of participants on various technical topics. Please note technical/AV requirements with submission.

Birds of a Feather

Birds of a Feather (BoF) sessions provide a dynamic, noncommercial venue for conference attendees to openly discuss current topics of interest to the RISC-V community. BoF sessions connect you with other attendees with similar interests. Come and help drive the conversation.


Strategic/visionary/forward thinking presentations. Typically 15 to 20 minutes in length.