RISC-V Summit is part of the Informa Tech Division of Informa PLC

This site is operated by a business or businesses owned by Informa PLC and all copyright resides with them. Informa PLC's registered office is 5 Howick Place, London SW1P 1WG. Registered in England and Wales. Number 3099067.

Informa

Mitesh Jain
Staff R&D Engineer at Synopsys Inc

Profile

At Synopsys, I am working on developing automated verification tools for sequential equivalence checking. I have eight plus years of industry experience in designing high-performance microprocessors and low-power DSP cores. I have worked on several aspects of the microprocessor design ranging from digital design, verification, and performance modeling. My main research is in mechanized formal verification and validation of  reactive systems.

Agenda Sessions

  • An Efficient Runtime Validation Framework based on the Theory of Refinement

    5:10pm