RISC-V Summit is part of the Informa Tech Division of Informa PLC

This site is operated by a business or businesses owned by Informa PLC and all copyright resides with them. Informa PLC's registered office is 5 Howick Place, London SW1P 1WG. Registered in England and Wales. Number 3099067.

Informa

Sven Beyer
Product Manager Design Verification at OneSpin Solutions

Profile

Sven Beyer has 19 years of experience in formal functional verification of complex hardware, with a focus on industrial processors. During his career, he has covered various roles involving methodology development, application, and product management. He has led the development of numerous formal verification IPs and apps, and holds several patents, including on processor verification. Dr. Beyer has led a number of successful industrial projects to perform the complete formal verification of processor cores, including superscalar implementations of Infineon's TriCore architecture. Most recently, he has overseen the development of the first formal verification IP for the complete verification of RISC-V based architectures. Crucially, this approach allows for proving the absence of unspecified behaviors using standard HDL languages and industry-proven tools. Prior to joining OneSpin, Dr. Beyer held a project management position for Verisoft, a large research project with 12 partners from industry and academia focused on the pervasive formal verification of computer systems. He holds a Dr.-Ing. (equivalent to a PhD) in computer science from Saarland University, Germany, achieved with a PhD thesis centered on the formal verification of an out-of-order processor.

Agenda Sessions

  • Poster Gallery on Expo Floor

    11:30am